Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 163
Functional Description
GC_DET# is grounded by the graphics card to indicate that it is an AGP 3.0-capable graphics
controller and is floated by an AGP 2.0 graphics controller. An AGP 2.0-only motherboard ignores
this signal. An AGP 3.0-capable motherboard uses this signal to select between a 0.35 V (AGP 3.0)
or 0.75 V (AGP 2.0) VREF. This VREF is sent back to the graphics controller card. The graphic
controller card can use the VREF level or the MB_DET# signal to determine the electrical mode.
MB_DET# is grounded by the motherboard to indicate that it is an AGP 3.0 capable motherboard,
and is floated by an AGP 2.0 motherboard. An AGP 2.0 only graphics controller ignores this
signal. An AGP 3.0 capable graphics controller uses the MB_DET# to select between 0.35 V
(AGP 3.0) or 0.75 V (AGP 2.0) VREF. This VREF signal level is sent back to the motherboard.
The motherboard board may use the VREF level or the GC_DET# signal to determine the
electrical mode. An AGP 2.0 graphics card supplies 0.75 V on AGPVREFGC at all times. A
universal card supplies 0.35 V or 0.75 V as selected by the MB_DET# signal.
An AGP 2.0 motherboard supplies 0.75 V AGPVREFGC at all times. A universal motherboard
supplies 0.35 V or 0.75 V, as selected by the GC_DET# signal.
The above description describes the typical case. Actual usage of the GC_DET# signal and
AGPVREFGC voltage by the motherboard is implementation dependant. Likewise, the actual
usage of the MB_DET# signal and AGPVREFGC voltage by the graphics controller is
implementation dependant. Optionally, the motherboard could use its own VREF which would be
switched by the GC_DET#.
The motherboard design is aware of its own capabilities and determines the graphics controller’s
capabilities from GC_DET#, as well as receiving the proper VREF voltage. Likewise, the graphics
controller design is also aware of its own capabilities and determines the motherboard’s
capabilities from MB_DET#, as well as receiving the proper VREF voltage.
5.4.10 AGP 3.0 Protocol
The MCH supports the AGP 8x protocol as specified in the AGP Specification 3.0. In AGP 8x
mode, the PIPE# signal cannot be used to enqueue transactions. The AGP 8x data rate provides a
theoretical maximum bandwidth of 2.13 GB/s. The actual bandwidth is determined by the memory
hit rate and other traffic to the memory controller.
5.4.11 AGP 2.0 Protocol
In addition to the 1x and 2x AGP protocols, the MCH supports 4x AGP read/write data transfers
and 4x sideband address generation. The 4x operation is compliant with the AGP 4x protocols as
described in the AGP Specification 3.0.