Hub Datasheet

120 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.7.30 APSIZE1—AGP Aperture Size Register (D1:F0)
Address Offset: 74–75h
Default Value: 0000h
Attribute: R/W
Size: 16 bits
This register determines the effective size of the Graphics Aperture used for a particular MCH
configuration. This register can be updated by the MCH-specific BIOS configuration sequence
before the PCI standard bus enumeration sequence takes place. If the register is not updated then a
default value will select an aperture of maximum size (i.e., 256 MB). The size of the table that will
correspond to a 256-MB aperture is not practical for most applications; therefore, these bits must
be programmed to a smaller practical value that will force adequate address range to be requested
via APBASE register from the PCI configuration software. Set by BIOS.
Bits
Default,
Access
Description
15:6 Reserved
5:0
00 0000b
R/W
Graphics Aperture Size (APSIZE). This register determines the aperture size. It
controls bits in the APBASE register, determining which bits are read/write or read only
such that PCI plug and play software will determine the proper size.
0 = When a bit in this register is a 0, the corresponding bit in the APBASE register will
become read only as a 0.
1 = When a bit in this register is a 1, the corresponding bit in the APBASE register will
be read/write.
There must be a single contiguous range of aperture sizes from the table below (i.e., No
gaps).
APSIZE1 bit 0 1 2 3 4 5
APBASE1 bit 22 23 24 25 26 27
Aperture size when
bits are 0
8 M (4 M,
when a 1)
16 M 32 M 64 M 128 M 256 M
11 10 9 8 7 6 5 4 3 2 1 0 Hex Aperture Size
1 1 1 1 0 0 1 1 1 1 1 1 F3F 4 MB
1 1 1 1 0 0 1 1 1 1 1 0 F3E 8 MB
1 1 1 1 0 0 1 1 1 1 0 0 F3C 16 MB
1 1 1 1 0 0 1 1 1 0 0 0 F38 32 MB
1 1 1 1 0 0 1 1 0 0 0 0 F30 64 MB
1 1 1 1 0 0 1 0 0 0 0 0 F20 128 MB
1 1 1 1 0 0 0 0 0 0 0 0 F00 256 MB