Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 119
Register Description
3.7.29 AGPCTRL1—AGP Control Register (D1:F0)
Address Offset: 70–73h
Default Value: 0000 0000h
Attribute: RO, R/W
Size: 32 bits
This register provides for additional control of the AGP interface. Set by drivers.
Bits
Default,
Access
Description
31:10 Reserved
90b
Calibration Disable.
0 = Enable.
1 = Disable. Calibration cycle operation is disabled by the core logic. Note that
calibration cycle should be automatically disabled by core-logic when not in AGP
3.0 signaling mode.
8 Reserved
7
0b
R/W
GTLB Enable (GTLBEN).
0 = Disable (default). GTLB is flushed by clearing the valid bits associated with each
entry. In this mode of operation all accesses that require translation bypass the
GTLB. All requests that are positively decoded to the graphics aperture force the
MCH to access the translation table in main memory before completing the
request. Translation table entry fetches will not be cached in the GTLB. When an
invalid translation table entry is read, this entry will still be cached in the GTLB
(ejecting the least recently used entry).
1 = Enable. Enables normal operations of the Graphics Translation Look aside Buffer.
NOTE: This bit can be changed dynamically (i.e., while an access to GTLB occurs);
however, the completion of the configuration write that asserts or deasserts
this bit will be delayed pending a complete flush of all dirty entries from the
write buffer. This delay will be incurred because this bit is used as a
mechanism to signal the chipset that the graphics aperture translation table is
about to be modified or has completed modifications. In the first case, all dirty
entries need to be flushed before the translation table is changed. In the
second case, all dirty entries need to be flushed because one of them is likely
to be a translation table entry which must be made visible to the GTLB by
flushing it to memory.
6:0 Reserved