Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 117
Register Description
3.7.28 AGPCMD—AGP Command Register (D1:F0)
Address Offset: 68–6Bh
Default Value: 0000 0000h
Attribute: RO, R/W
Size: 32 bits
This register provides control of the AGP operational parameters. Set by drivers.
Bits
Default,
Access
Description
31:13 Reserved
12:10
000b
R/W
Programmed Calibration Period (PCAL_Cycle). These bits are programmed with the
period for core-logic initiated bus cycles for calibrating the I/O buffers for both master
and target. The default value is based on the MCH requirement. This value is updated
with the smaller of the value in CAL_CYCLE from the master’s and target’s AGPSTAT
register. Note that the MCHTST register bits 31:30 must be set to 2 ms for the setting in
this register to be correct.
000 = 4 ms
001 = 16 ms
010 = 64 ms
011 = 256 ms
100–111 = Reserved for future use
9
0b
R/W
Side Band Addressing Enable (SBAEN).
0 = Disable
1 = Enable. Side band addressing mechanism is enabled.
NOTE: In AGP 3.0 signaling mode this bit is ignored as sideband addressing is the
only allowed mechanism
8
0b
R/W
AGP Enable (AGPEN). This bit enables/disables AGP. This bit also determines which
device register set (Device 0 or Device 1) is used for AGP.
0 = Disable. MCH ignores all AGP operations, including the sync cycle. Any AGP
operations received while this bit is set to 1 will be serviced even if this bit is reset
to 0. If this bit transitions from 1-to-0 on a clock edge in the middle of an SBA
command being delivered in 1x mode, the command will be issued. Device 0
register set is used.
1 = Enable. MCH responds to AGP operations delivered via PIPE# (AGP 2.0 signaling
mode), or to operations delivered via SBA if the AGP side band enable bit is also
set to 1. Device 1 register set is used.
NOTE: This bit and the AGPEN bit in device 0 should not be set at the same time.
7
0b
RO
64-bit GART Support (GART64B). Hardwired to 0. This indicates that the MCH
supports only 32-bit GART entries (which are sufficient for 36-bit addressing). This bit
also determines which register set (Device 0 set or Device 1 set) is used for AGP. When
this bit is a 0, the Device 0 register set is used.
6 Reserved
5
0b
RO
Over 4-GB Support (OVER4G). Hardwired to 0. MCH does not support addresses
greater than 4 GB in AGP.