Hub Datasheet
Intel
®
E7505 Chipset MCH Datasheet 101
Register Description
3.7.4 PCISTS1—PCI Status Register (D1:F0)
Address Offset: 06–07h
Default Value: 00A0h/00B0h
Attribute: RO, R/WC
Size: 16 bits
PCISTS1 is a 16-bit status register that reports the occurrence of error conditions associated with
primary side of the virtual PCI-to-PCI bridge embedded within the MCH.
Bits
Default,
Access
Description
15
0b
RO
Detected Parity Error (DPE). Hardwired to 0. Parity is not supported on the primary
side of this device.
14
0b
R/WC
Signaled System Error (SSE). ‘
0 = MCH Device 1 did Not generated an SERR message over HI_A for any enabled
Device 1 error condition.
1 = MCH Device 1 generated an SERR message over HI_A for any enabled Device 1
error condition. Device 1 error conditions are enabled in the ERRCMD, PCICMD1
and BCTRL1 registers. Device 1 error flags are read/reset from the ERRSTS and
SSTS1 register.
NOTE: Software clears this bit by writing a 1 to it.
13
0b
RO
Received Master Abort Status (RMAS). Hardwired to 0. The concept of a master abort
does not exist on primary side of this device.
12
0b
RO
Received Target Abort Status (RTAS). Hardwired to 0. The concept of a target abort
does not exist on primary side of this device.
11
0b
RO
Signaled Target Abort Status (STAS). Hardwired to 0. The concept of a target abort
does not exist on primary side of this device.
10:9
00b
RO
DEVSEL# Timing (DEVT). Hardwired to 00. The MCH does not support subtractive
decoding devices on bus 0. therefore, this bit is hardwired to 00 to indicate that device 1
uses the fastest possible decode.
8
0b
RO
Data Parity Detected (DPD). Hardwired to 0. Parity is not supported on the primary side
of this device.
7
1b
RO
Fast Back-to-Back (FB2B). Hardwired to 1. This indicate that the AGP interface always
supports fast back to back writes.
6 Reserved
5
1b
RO
66/60 MHz capability (CAP66). Hardwired to 1. This indicates that the AGP/PCI bus is
66 MHz capable.
4
0b or 1b
RO
Capability List (CLIST). When this bit is set to 1, it indicates to the configuration
software that this device/function implements a list of new capabilities. A list of new
capabilities is accessed via register CAPPTR at configuration address offset 34h.
Register CAPPTR contains an offset pointing to the start address within configuration
space of this device where the AGP 8x Capability standard register resides.
This bit is read only, and is set by BIOS.
3:0 Reserved