Datasheet

DRAM Controller Registers (D0:F0)
70 Datasheet
5.1.5 RID—Revision Identification
B/D/F/Type: 0/0/0/PCI
Address Offset: 8h
Default Value: See table below
Access: RO
Size: 8 bits
This register contains the revision number of the MCH Device 0. These bits are read
only and writes to this register have no effect.
5.1.6 CC—Class Code
B/D/F/Type: 0/0/0/PCI
Address Offset: 9–Bh
Default Value: 060000h
Access: RO
Size: 24 bits
This register identifies the basic function of the device, a more specific sub-class, and a
register-specific programming interface.
5.1.7 MLT—Master Latency Timer
B/D/F/Type: 0/0/0/PCI
Address Offset: Dh
Default Value: 00h
Access: RO
Size: 8 bits
Device 0 in the MCH is not a PCI master. Therefore this register is not implemented.
Bit Access
Default
Value
Description
7:0 RO
See
description
Revision Identification Number (RID): This is an 8-bit value that
indicates the revision identification number for the MCH Device 0. Refer to
the Intel
®
3200 and 3210 Chipset Specification Update for the value of this
register.
Bit Access
Default
Value
Description
23:16 RO 06h
Base Class Code (BCC): This is an 8-bit value that indicates the base class
code for the MCH. This code has the value 06h, indicating a Bridge device.
15:8 RO 00h
Sub-Class Code (SUBCC): This is an 8-bit value that indicates the category of
Bridge into which the MCH falls. The code is 00h indicating a Host Bridge.
7:0 RO 00h
Programming Interface (PI): This is an 8-bit value that indicates the
programming interface of this device. This value does not specify a particular
register set layout and provides no practical use for this device.
Bit Access
Default
Value
Description
7:0 RO 00h Reserved