Datasheet

Datasheet 109
DRAM Controller Registers (D0:F0)
5.2.13 C0CKECTRL—Channel 0 CKE Control
B/D/F/Type: 0/0/0/MCHBAR
Address Offset: 260–263h
Default Value: 00000800h
Access: RW, RW/L, RO
Size: 32 bits
This register provides CKE controls for Channel 0.
Bit Access
Default
Value
Description
31:28 RO 0000b Reserved
27 RW 0b
Start the Self-Refresh Exit Sequence (sd0_cr_srcstart): This field indicates
the request to start the self-refresh exit sequence
26:24 RW 000b
CKE Pulse Width Requirement in High Phase (sd0_cr_cke_pw_hl_safe):
This field indicates CKE pulse width requirement in high phase. This field
corresponds to t
CKE
(high) in the DDR specification.
23 RW/L 0b
Rank 3 Population (sd0_cr_rankpop3):
1 = Rank 3 populated
0 = Rank 3 not populated
This register is locked by ME stolen Memory lock.
22 RW/L 0b
Rank 2 Population (sd0_cr_rankpop2):
1 = Rank 2 populated
0 = Rank 2 not populated
This register is locked by ME stolen Memory lock.
21 RW/L 0b
Rank 1 Population (sd0_cr_rankpop1):
1 = Rank 1 populated
0 = Rank 1 not populated
This register is locked by ME stolen Memory lock.
20 RW/L 0b
Rank 0 Population (sd0_cr_rankpop0):
1 = Rank 0 populated
0 = Rank 0 not populated
This register is locked by ME stolen Memory lock.
19:17 RW 000b
CKE Pulse Width Requirement in Low Phase (sd0_cr_cke_pw_lh_safe):
This configuration register indicates CKE pulse width requirement in low phase.
This field corresponds to t
CKE
(low) in the DDR specification.
16 RW 0b
Enable CKE Toggle for PDN Entry/Exit (sd0_cr_pdn_enable): This bit
indicates that the toggling of CKEs (for PDN entry/exit) is enabled.
15:14 RO 00b Reserved
13:10 RW 0010b
Minimum Powerdown exit to Non-Read command spacing (sd0_cr_txp):
This field indicates the minimum number of clocks to wait following assertion of
CKE before issuing a non-read command.
1010–1111 = Reserved.
0010–1001 = 2–9clocks.
0000–0001 = Reserved.
9:1 RW
0000000
00b
Self Refresh Exit Count (sd0_cr_slfrfsh_exit_cnt): This field indicates the
Self refresh exit count. (Program to 255). This field corresponds to t
XSNR
/t
XSRD
in the DDR Specification.
0RW0b
Indicates only 1 DIMM Populated (sd0_cr_singledimmpop): This field
indicates the that only 1 DIMM is populated.