Specification Update

Errata
48 Intel
®
Xeon
®
Processor E7 v2 Product Family
Specification Update January 2015
condition: IOH will set Command Completed bit after delivering the new commands
written in the Slot Controller register (offset A8h) to VPP. The IOH detects new
commands written in Slot Control register by checking the change of value for Power
Controller Control (bit[10]), Power Indicator Control (bits[9:8]), Attention Indicator
Control (bits[7:6]), or Electromechanical Interlock Control (bit[11]) fields. Any other
configuration writes to the Slot Control register without changing the values of these
fields will not cause Command Completed bit to be set.
The PCIe Base Specification Revision 2.0 or later describes the “Slot Control Register”
in section 7.8.10, as follows (Reference section 7.8.10, Slot Control Register, Offset
18h). In hot-plug capable Downstream Ports, a write to the Slot Control register must
cause a hot-plug command to be generated (see Section 6.7.3.2 for details on hot-plug
commands). A write to the Slot Control register in a Downstream Port that is not hot-
plug capable must not cause a hot-plug command to be executed.
The PCIe Spec intended that every write to the Slot Control Register is a command and
expected a command complete status to abstract the VPP implementation specific
nuances from the OS software. IOH PCIe Slot Control Register implementation is not
fully conforming to the PCIe Specification in this respect.
Implication: Software checking on the Command Completed status after writing to the Slot Control
register may time out.
Workaround: Software can read the Slot Control register and compare the existing and new values to
determine if it should check the Command Completed status after writing to the Slot
Control register.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF119 Platform Recovery After a Machine Check May Fail
Problem: While attempting platform recovery after a machine check (as indicated by CATERR#
signaled from the legacy socket), the original error condition may prevent normal
platform recovery which can lead to a second machine check. A remote processor
detecting a second Machine Check Event will hang immediately
Implication: Due to this erratum, it is possible a system hang may be observed during a warm reset
caused by a CATERR#.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF120 PECI May be Non-responsive When System is in BMC Init Mode
Problem: The allow_peci_pcode_error_rsp field in the DYNAMIC_PERF_POWER_CTL CSR (Device
10; Function 2; Offset 0x64H; bit 16) does not retain its value after a warm reset.
When the system is in BMC Init mode, this erratum can cause PECI (Platform
Environment Control Interface) access to be non-responsive after a warm reset caused
by a Machine Check Event.
Implication: When this erratum occurs, PECI requests will return a status of 91H, indicating that the
request could not be processed.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF121 A CATERR# May Be Observed During Warm Reset when Intel SMI2
Clock Stop is Enabled
Problem: When Intel SMI2 clock stop is enabled by setting the disble_vmse_pc6 field in the
VMSE_PC6_CNTL_0 CSR (Device 16/30; Function 2, 6; Offset 0x620H; bit 31) to 1, the
processor may not complete a warm reset.
Implication: When this erratum occurs, a CATERR# is signaled with IA32_MCi_STATUS.MCACOD =
0x0D.