Specification Update

Errata
Intel
®
Xeon
®
Processor E7 v2 Product Family 47
Specification Update January 2015
Implication: Due to Intel® Turbo Boost Technology using the Power Meter to compare instantaneous
power consumption to the rated TDP, the core frequency in P0 may set to a ratio where
the processor exceeds its rated TDP. Further, using the average power limit facility
(RAPL) may cause the processor to run at a power consumption level that is higher
than expected.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF114 DTS2.0 May Report Inaccurate Temperature Margin
Problem: When DTS (Digital Thermal Sensor) 2.0 is enabled on the E5-4600 v2 product family,
the thermal margin reported by the PACKAGE_THERM_MARGIN MSR (1A1H)
THERMAL_MARGIN bits [15:0] may be inaccurate.
Implication: Due to this erratum, fan speed control algorithms may set the fan speed incorrectly.
Workaround: It is possible for BIOS to contain processor configuration data and code changes as a
workaround for this erratum.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF115 A DMI UR May Unexpectedly Cause a CATERR# After a Warm Reset
Problem: Reset disables certain error detection facilities to prevent error signaling from
interfering with system initialization. Due to this erratum, DMI UR (Unsupported
Request) error reporting, if previously enabled by BIOS, is not disabled by a
warm reset.
Implication: A platform event shortly after a warm reset that produces a DMI UR is subject to this
erratum. When this erratum occurs, a CATERR# is signaled with
IA32_MCi_STATUS.MCACOD = 0xE0B. Some platforms automatically reset after a
CATERR# so this erratum may be seen as an unexpected re-boot.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF116 PECI May Not be Able to Access IIO CSRs
Problem: Due to this erratum, when the processor has viral enabled and an uncorrectable error
occurs in the core, PECI (Platform Environment Control Interface) may not be able to
access IIO (Integrated I/O) CSRs.
Implication: When this erratum occurs, IIO CSR access using a PECI RdPCIConfigLocal() or
WrPCIConfigLocal() command will return a status of 91H, indicating that the request
could not be processed.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF117 Spurious Patrol Scrub Errors Observed During a Warm Reset
Problem: The patrol scrub engine continues to run during a warm reset; this can lead to spurious
errors being reported by the Memory Controller while memory is in Self Refresh.
Implication: Due to this erratum, erroneous patrol scrub errors may be observed during a
warm reset.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF118 PCIe Slot Status Register Command Completed bit not always updated
on any configuration write to the Slot Control Register
Problem: For PCIe root ports (devices 0 - 10) supporting hot-plug, the Slot Status Register
(offset AAh) Command Completed (bit[4]) status is updated under the following