Specification Update

Errata
Intel
®
Xeon
®
Processor E7 v2 Product Family 27
Specification Update January 2015
CF31 Routing Intel
®
High Definition Audio Traffic Through VC1 May Result
in System Hang.
Problem: When bit 9 in the IIOMISCCTRL CSR (Bus 0; Device 5; Function 0; Offset 1C0H) is set,
VCp inbound traffic (Intel
®
HD Audio) is routed through VC1 to optimize isochronous
traffic performance. Due to this erratum, VC1 may not have sufficient bandwidth for all
traffic routed through it; overflows may occur.
Implication: This erratum can result in lost completions that may cause a system hang.
Workaround: A BIOS workaround has been identified. Refer to the Intel® Xeon® Processor E7 v2
Product Family-based Platform CPU/Intel QPI/Memory Reference Code version 1.0 or
later and release notes.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF32 Patrol Scrubbing does not Skip Ranks Disabled After DDR Training.
Problem: If a rank is detected as failed after completing DDR training then BIOS will mark it as
disabled. Disabled ranks are omitted from the OS memory map. Due to this erratum, a
rank disabled after DDR training completes is not skipped by the Patrol Scrubber. Patrol
Scrubbing of the disabled ranks may result in superfluous correctable and
uncorrectable memory error reports.
Implication: Disabling ranks after DDR training may result in the over-reporting of memory errors.
Workaround: A BIOS workaround has been identified. Refer to the Intel® Xeon® Processor E7 v2
Product Family-based platform CPU/Intel QPI/Memory Reference Code version 1.0 or
later and release notes.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF33 DR6.B0-B3 May Not Report All Breakpoints Matched When a MOV/POP
SS is Followed by a REP MOVSB or STOSB
Problem: Normally, data breakpoints matches that occur on a MOV SS, r/m or POP SS will not
cause a debug exception immediately after MOV/POP SS but will be delayed until the
instruction boundary following the next instruction is reached. After the debug
exception occurs, DR6.B0-B3 bits will contain information about data breakpoints
matched during the MOV/POP SS as well as breakpoints detected by the following
instruction. Due to this erratum, DR6.B0-B3 bits may not contain information about
data breakpoints matched during the MOV/POP SS when the following instruction is
either an REP MOVSB or REP STOSB.
Implication: When this erratum occurs, DR6 may not contain information about all breakpoints
matched. This erratum will not be observed under the recommended usage of the MOV
SS,r/m or POP SS instructions (that is, following them only with an instruction that
writes (E/R)SP).
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF34 64-bit REP MOVSB/STOSB May Clear The Upper 32-bits of RCX, RDI
And RSI Before Any Data is Transferred
Problem: If a REP MOVSB/STOSB is executed in 64-bit mode with an address size of 32 bits, and
if an interrupt is being recognized at the start of the instruction operation, the upper
32-bits of RCX, RDI and RSI may be cleared, even though no data has yet been copied
or written.
Implication: Due to this erratum, the upper 32-bits of RCX, RDI and RSI may be prematurely
cleared.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the affected steppings, see the “Summary Table of Changes”.