Guidelines

Introduction
8 Intel
®
7500 Chipset Thermal Mechanical Design Guide
1.2 Definition of Terms
FC-BGA Flip Chip Ball Grid Array. A package type defined by a plastic substrate where
a die is mounted using an underfill C4 (Controlled Collapse Chip Connection)
attach style. The primary electrical interface is an array of solder balls
attached to the substrate opposite the die. Note that the device arrives at
the customer with solder balls attached.
BLT Bond Line Thickness. Final settled thickness of the thermal interface
material after installation of heatsink.
IOH Input Output Hub. The IO Controller Hub component that contains the
Intel® QuickPath Interconnect (Intel® QPI) interface to the processor, and
PCI Express* interface. It communicates with the Intel® 82801Ix I/O
Controller Hub (ICH9) over a proprietary interconnect called the Enterprise
South Bridge Interface (ESI).
T
case_max
Die temperature allowed. This temperature is measured at the geometric
center of the top of the die.
TDP Thermal design power. Thermal solutions should be designed to dissipate
this target power level. TDP is not the maximum power that the IOH can
dissipate.
1.3 Reference Documents
The reader of this specification should also be familiar with material and concepts
presented in the following documents:
Note: Unless otherwise specified, these documents are available through your Intel field sales
representative. Some documents may not be available at this time.
§
Title Document # Location
Intel
®
7500 Chipset Datasheet 322827 www.intel.com
Various system thermal design suggestions
(http://www.formfactors.org)