Specification Update

10 Intel
®
E7320 Memory Controller Hub (MCH) Specification Update
Errata
Errata
1. Data corruption after an illegal front side bus configuration Write
Problem: When an illegal FSB configuration write occurs (bits [30:24] of the Configuration Address
Register (CONFIG_ADDRESS, I/O address 0CF8h) are non-zero) PCI configuration accesses
following this write may be corrupted.
Implication: This is a mishandled error case and causes corruption of transactions after this transaction. This is
an illegal case.
Workaround: Do not write non-zero values to the PCI configuration address register reserved fields.
Status: For the steppings effected, see the Summary Table of Changes.
2. Improper ECC and Memory Initialization while in Symmetric mode
Problem: ECC and memory initialization is not properly executed when the MCH is in Symmetric
Addressing mode. The MCH automatically enters symmetric address bit permuting when precisely
four identical ranks of memory are available.
Implication: Correctable and uncorrectable memory errors may be detected since ECC is not properly
initialized. The entire memory array is not initialized with zeros.
Workaround: Refer to your Intel representative for details
Status: For the steppings effected, see the Summary Table of Changes.
3. Single Channel ECC Error Injection issue
Problem: In single channel mode, single ECC error injection to Quad-word 4/5 or Quad-word 6/7 is not
functional. The “Inject all” function works for all Quad-words as expected, as do all injection cases
in dual channel mode.
Implication: Injected errors will not propagate to the memory array. As a result, when the memory location is
read, the Correctable Read Memory Error Channel B and Correctable Read Memory Error Channel
A of the DRAM_FERR Register (Device 0, Function 1, Offset 80h bit 0 and 8 Respectively) report
no errors.
Workaround: Use “inject always” or limit error injection via the ECCDIAG register to the first half of the cache
line when in single channel mode.
Status: For the steppings effected, see the Summary Table of Changes.
4. PCI Express* add-in card presence detect state misreported
Problem: PCI Express ports that are configured as non-hot plug capable incorrectly assert the add-in card
Presence Detect State in the PCI Express Slot Status Register (EXP_SLTSTS Device 2-3, Function
0, Offset 7E-7Fh bit 6) regardless of the presence of an add-in card.
Implication: Software may interpret the presence of an add-in card when none exists.
Workaround: Utilize the Link Active bit in the Vendor Specific Status Register 1(VS_STS1 Device 2-3, Function
0, Offset 47h bit 1) as an alternative to the Presence Detect State bit.
Status: For the steppings effected, see the Summary Table of Changes.