Vol 1

Electrical Specifications
72 Intel® Xeon® Product 2800/4800/8800 v2 Product Family
Datasheet Volume One, February 2014
6.1.9.2 Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the Intel® Xeon®
E7 v2 processor is capable of generating large current swings between low and full
power states. This may cause voltages on power planes to sag below their minimum
values if bulk decoupling is not adequate. Large electrolytic bulk capacitors (C
BULK
),
help maintain the output voltage during current transients, for example coming out of
an idle condition. Care must be taken in the baseboard design to ensure that the
voltages provided to the processor remain within the specifications listed in Table 6-12.
Failure to do so can result in timing violations or reduced lifetime of the processor.
6.1.9.3 Voltage Identification (VID)
The reference voltage or the VID setting is set via the SVID communication bus
between the processor and the voltage regulator controller chip. The VID settings are
the nominal voltages to be delivered to the processor's V
CC and
V
SA
lands when current
draw equals zero. Table 6-3 specifies the reference voltage level corresponding to the
VID value transmitted over serial VID. The voltage will change due to temperature
and/or current load changes in order to minimize the power and to maximize the
performance of the part. The specifications are set so that a voltage regulator can
operate with all supported frequencies.
Individual processor VID values may be calibrated during manufacturing such that two
processor units with the same core frequency may have different default VID settings.
The Intel® Xeon® E7 v2 processor uses voltage identification signals to support
automatic selection of V
CC and
V
SA
power supply voltages. If the processor socket is
empty (SKTOCC_N high), or a “not supported” response is received from the SVID bus,
then the voltage regulation circuit cannot supply the voltage that is requested, the
voltage regulator must disable itself or not power on. Vout MAX register (30h) is
programmed by the processor to set the maximum supported VID code and if the
programmed VID code is higher than the VID supported by the VR, then VR will
respond with a “not supported” acknowledgement.
Table 6-1. Power and Ground Lands
Power and
Ground Lands
Number of
Lands
Comments
V
CC
218 Each V
CC
land must be supplied with the voltage determined by the
SVID Bus signals. Table 6-3 Defines the voltage level associated with
each core SVID pattern.Table 6-12, Figure 6-2, and Figure 6-4
represent V
CC
static and transient limits. VCC has a VBOOT setting of
0.0 V.
V
CC33
1V
CC33
supplies a fixed 3.3 volt stand by voltage to supply PIROM and
the OEM scratch ROM.
V
CCPLL
3Each V
CCPLL
land is connected to a variable 1.80 V supply, power the
Phase Lock Loop (PLL) clock generation circuitry. An on-die PLL filter
solution is implemented within the Intel® Xeon® E7 v2 processor.
V
VMSE_01
V
VMSE_23
16 Provides power to the processor SMI2 interface with fixed 1.35 V
supply.
V
TT
43 V
TT,
including lands VTTA, and VTTQ must be supplied by a fixed
1.00 V supply.
V
SA
12 Each V
SA
land must be supplied with the voltage determined by the
SVID Bus signals. VSA has a VBOOT setting of 0.9 V.
V
SS
726 Ground