Vol 1

6 Intel® Xeon® Processor E7-8800/4800/2800 v2 Product Family
Datasheet Volume One, February 2014
4-8 DTS: 105W 12 - 15 Core Thermal Profile...............................................................54
4-9 DTS: 105W 8 - 10 Core Thermal Profile ................................................................55
4-10 DTS: 105W 6 Core Thermal Profile.......................................................................56
4-11 Case Temperature (TCASE) Measurement Location.................................................57
4-12 Frequency and Voltage Ordering..........................................................................59
6-1 Input Device Hysteresis......................................................................................70
6-2 VR Power-State Transitions.................................................................................75
6-3 VCC Static and Transient Tolerance Loadlines Intel® Xeon® E7 v2 Processor ............87
6-4 Load Current Versus Time...................................................................................88
6-5 VCC Overshoot Example Waveform......................................................................89
6-6 Electrical Test Circuit..........................................................................................97
6-7 VMSE Command / Control and Clock Timing Waveform...........................................98
6-8 VMSE Clock to Output Timing Waveform...............................................................98
6-9 VMSE Clock to DQS_DN Skew Timing Waveform ....................................................98
6-10 BCLK{0/1} Differential Clock Crosspoint Specification.............................................99
6-11 BCLK{0/1} Differential Clock Measurement Points for Duty Cycle and Period .............99
6-12 BCLK{0/1} Differential Clock Measurement Points for Edge Rate..............................99
6-13 BCLK{0/1} Differential Clock Measurement Point for Ringback...............................100
6-14 BCLK{0/1} Single Ended Clock Measurement Points for Absolute Cross Point
and Swing ......................................................................................................100
6-15 BCLK{0/1} Single Ended Clock Measurement Points for Delta Cross Point................100
6-16 SMBus Timing Waveform ..................................................................................101
6-17 BCLK to JTAG/TAP Signals Output Valid Delay......................................................101
6-18 JTAG/TAP Output Valid Delay Timing Waveform...................................................101
6-19 PROCHOT_N Setup and Hold Timing Waveforms ..................................................102
6-20 Serial VID Interface (SVID) Signals Clock Timings................................................102
6-21 Fault Resilient Booting (FRB) Timing Requirements...............................................103
6-22 Voltage Sequence Timing Requirements..............................................................104
6-23 MEM_HOT_C{01/23}_N Event Assertion Waveform..............................................105
6-24 PWRGOOD Signal Waveform .............................................................................106
6-25 Maximum Acceptable Overshoot/Undershoot Waveform ........................................108
8-1 Processor Package Assembly Sketch...................................................................159
8-2 Processor Package Drawing Sheet 1 of 2.............................................................161
8-3 Processor Package Drawing Sheet 2 of 2.............................................................162
8-4 Processor Top-Side Markings ............................................................................164
Tables
1-1 Processor Documents.........................................................................................20
1-2 Public Specifications...........................................................................................20
3-1 System States...................................................................................................31
3-2 Package C-State Support....................................................................................31
3-3 Core C-State Support.........................................................................................32
3-4 System Memory Power States .............................................................................32
3-5 DMI2/PCI Express Link States .............................................................................33
3-6 Intel® QPI States..............................................................................................33
3-7 G, S and C State Combinations............................................................................33
3-8 P_LVLx to MWAIT Conversion..............................................................................36
3-9 Coordination of Core Power States at the Package Level..........................................38
4-1 Intel® Xeon® E7v2 Processor SKU Summary Table ...............................................45
4-2 Tcase: 155W Thermal Specifications.....................................................................45