Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 95
Register Description
3.6.26 SCICMD_DRAM —SCI Command Register (D0:F1)
Address Offset: 88h
Default Value: 00h
Sticky No
Attribute: RO, R/W
Size: 8 bits
This register determines whether SCI will be generated when the associated flag is set in the
DRAM_FERR or DRAM_NERR Register. When an error flag is set in the DRAM_FERR or
DRAM_NERR Registers, it can generate an SERR, SMI, or SCI when enabled in the SERRCMD,
SMICMD, or SCICMD Registers, respectively. Only one message type can be enabled.
3.6.27 SMICMD_DRAM—SMI Command Register (D0:F1)
Address Offset: 8Ah
Default Value: 00h
Sticky No
Attribute: RO, R/W
Size: 8 bits
This register determines whether SMI will be generated when the associated flag is set in the
DRAM_FERR or DRAM_NERR Register. When an error flag is set in the DRAM_FERR or
DRAM_NERR Register, it can generate an SERR, SMI, or SCI when enabled in the SERRCMD,
SMICMD, or SCICMD Registers, respectively. Only one message type can be enabled.
Bits
Default,
Access
Description
7:2 Reserved
1
0b
R/W
SCI on Multiple-Bit DRAM ECC Error (DMERR).
0 = Disable.
1 = Enable. The MCH generates an SCI when it detects a multiple-bit error reported by
the DRAM controller.
0
0b
R/W
SCI on Single-Bit DRAM ECC Error (DSERR).
0 = Disable.
1 = Enable. The MCH generates an SCI when the DRAM controller detects a single-bit
error.
Bits
Default,
Access
Description
7:2 Reserved
1
0b
R/W
SMI on Multiple-Bit DRAM ECC Error (DMERR).
0 = Disable.
1 = Enable. The MCH generates an SMI when it detects a multiple-bit error reported
by the DRAM controller.
0
0b
R/W
SMI on Single-Bit DRAM ECC Error (DSERR).
0 = Disable.
1 = Enable. The MCH generates an SMI when the DRAM controller detects a single-
bit error.