Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 27
Signal Description
CS_A[5:0]#
O
SSTL-2
Chip Select: The chip select inputs determine which row a command is
targeting. There is one per row (2 per DIMM).
Multiplexed Chip Selects and clocks: These signals are chip select
outputs on a three-DIMM motherboard supporting registered DIMMs only,
and clock outputs on a two DIMM motherboard which supports unbuffered
or registered DIMMs. A configuration bit determines their function. The
default function is chip selects.
• CK2/CK2# are at pins 76 and 75 of the DIMM.
MA_A[13:0]
O
SSTL-2
Memory Address: These signals provide the row address for ACTIVE
commands, and the column address and auto-precharge bit for read/write
commands, to select one location out of the memory array in the respective
bank. MA_A10 is sampled during a precharge command to determine
whether the precharge applies to one bank (MA_A10 low) or all banks
(MA_A10 high). If only one bank is to be Precharge, the bank is selected by
BA_A0, BA_A1. The address inputs also provide the opcode during a Mode
Register Set command. BA_A0 and BA_A1 define which mode register is
loaded during the Mode Register Set command (MRS or EMRS).
BA_A[1:0]
O
SSTL-2
Bank Address: The Bank Address specifies which bank that an activate,
read, write, or precharge command is targeting.
RAS_A#
O
SSTL-2
Row Address Strobe: This signal is used to indicate an activate command,
opening a page specified by the MA signals in the bank specified by the
BA_x signals. Used with WE_A# to indicate a precharge command, closing
the page in the bank specified by the BA_x signals. RAS_A# is also used to
enter register set mode or start an auto refresh or enter self refresh.
CAS_A#
O
SSTL-2
Column Address Strobe: This signal is used to indicate a read or write
command to the open page in the bank specified by the BA_x signals.
CAS_A# is also used to enter register set mode or start an auto refresh or
enter self refresh.
WE_A#
O
SSTL-2
Write Enable: This signal is used to differentiate a read from a write
command when CAS_A# is active and RAS_A# is inactive. it is used to
differentiate an activate command when RAS_A# is active and CAS_A# in
inactive. WE_A# is also used to terminate a burst, enter register set mode.
Table 2-2. DDR Channel A Signals (Sheet 2 of 3)
Signal Name Type Description
Signal 2 DIMM 3 DIMM
CS_A5#/CMDCLK_A6 DIMM 2 S1#
CS_A4#/CMDCLK_A6# DIMM 2 S0#
CS_A3# DIMM 1 S1# DIMM 1 S1#
CS_A2# DIMM 1 S0# DIMM 1 S0#
CS_A1# DIMM 0 S1# DIMM 0 S1#
CS_A0# DIMM 0 S0# DIMM 0 S0#