Hub Datasheet

18 Intel
®
E7505 Chipset MCH Datasheet
Introduction
1.3 Intel
®
E7505 Chipset System Architecture
The Intel
®
E7505 chipset is optimized for the Intel
®
Xeon™ processor with 512 KB L2 cache. The
architecture of the chipset provides the performance and feature-set required for dual-processor
based workstations in the volume and performance market segments. The MCH supports AGP 8x
with backwards compatibility to AGP 4x. The AGP interface is fully compliant with the AGP
Specification 3.0. The system bus, used to connect the processor with the Intel
®
E7505 chipset,
utilizes a 400 MHz/533 MHz transfer rate for data transfers, delivering a bandwidth of 4.27 GB/s.
The Intel
®
E7505 chipset architecture supports a 144-bit wide, 266 MHz Double Data Rate (DDR)
memory interface also capable of transferring data at 4.27 GB/s (see Table 1-1). The memory
interface supports dual channel DDR system memory with registered or unbuffered SDRAM
DIMMs. The hub interface 2.0 (HI2.0), a chipset component interconnect, is designed into the
Intel
®
E7505 chipset to provide more efficient communication between chipset components for
high-speed I/O. The HI2.0 connection provides 1.066 GB/s I/O bandwidth and can be used for
PCI-X via the P64H2 hub component.
In addition to these performance features, Intel
®
E7505 chipset-based platforms also provide the
RAS (Reliability, Availability, Serviceability) features required for volume and performance
workstations. These features include: Intel
®
x4 Single Device Data Correction (x4 SDDC)
technology ECC for memory, ECC for all high-performance I/O, SMBus interface, and processor
thermal monitoring.
The Intel
®
E7505 chipset consists of three major components: the Memory Controller Hub (MCH),
the I/O Controller Hub 4 (ICH4), and the PCI/PCI-X 64-bit Hub 2.0 (P64H2). The MCH’s I/O
interfaces consists of both a HI2.0 and a HI1.5 interface. The chipset components communicate via
hub interfaces (HIs). The MCH provides two hub interface connections: one for the ICH4 and one
for high-speed I/O using a P64H2 bridge. The P64H2 provides bridging functions between HI_B
and the PCI / PCI-X bus.
Additional platform features supported by the Intel
®
E7505 chipset include four ATA/100 IDE
drives, Low Pin Count interface (LPC), integrated LAN Controller, Audio Codec, and Universal
Serial Bus (USB).
The Intel
®
E7505 chipset is also ACPI compliant and supports Full-on, Stop Grant, Suspend to
Disk, and Soft-off power management states. Through the use of an appropriate LAN device, the
Intel
®
E7505 chipset also supports wake-on-LAN* for remote administration and troubleshooting.
Table 1-1. Supported Memory Modes
SB MT/s
SB Clock
MHz
SB BW DDR MT/s
DDR Clock
MHz
DDR BW
533 133 4.3 GB/sec 266 133 4.3 GB/sec
400 100 3.2 GB/sec 200 100 3.2 GB/sec
Table 1-2. DIMM Support
Type Unbuffered Registered
Dual Channel 1 to 2 pair DIMMs (4 rows) 1 to 3 pair DIMMs (6 rows max)