Hub Datasheet

16 Intel
®
E7505 Chipset MCH Datasheet
Introduction
1.2 Reference Documents
Intel
®
P64H2
The PCI-64 Hub 2 component adds PCI-X functionality to the chipset.The P64H2
connects to the MCH over a proprietary interconnect called the Hub Interface 2.0.
The P64H2 can be configured as two 64-bit 100 MHz PCI-X interfaces or a single
64-bit 133 MHz PCI-X interface.
Power Good Reset All MCH is reset, including sticky registers. This state looks like initial power on.
Primary PCI or PCI_A
The physical PCI bus is driven directly by the ICH4 component. The PCI_A bus
supports up to six PCI 2.2 compliant components which operate at 5 V, 32-bit, and
33 MHz. Communication between PCI_A and the MCH occurs over HI_A.
NOTE: The Primary PCI bus is referred to as PCI_A is not PCI Bus #0 from a
configuration standpoint.
SB
The processor system bus operates at either 133 MHz or 100 MHz system bus
clock.
SDDC
Intel
®
x4 Single Device Data Correction (x4 SDDC). In a x4 DDR memory device,
SDDC provides error detection and correction for 1, 2, 3, or 4 data bits within that
single device and provides error detection, up to 8 data bits, within two devices.
SEC-DED
Single Error Correct-Double Error Detect system memory error correction circuitry
supported by the MCH.
System Reset Also called reset, the MCH logic is reset except for certain sticky registers.
Title Document/Location
Intel
®
Xeon™ Processor and Intel
®
E7505 Chipset Platform Design Guide 251934
Intel
®
82801BA I/O Controller Hub 4 (ICH4) Datasheet 290744
Intel
®
82870P2 PCI/PCI-X 64 Bit Hub 2 (P64H2) Datasheet 290732
Intel
®
E7505 Chipset Memory Controller Hub Specification Update
251933 / http://
developer.intel.com/design/
chipsets/e7505/
Intel
®
NetBurst™ Microarchitecture BIOS Writer's Guide Note 1
Intel
®
E7500/E7505 Chipset Memory Controller Hub (MCH) Thermal Design
Guidelines
298647
CK408 Clock Synthesizer/Driver Specification Note 1
Accelerated Graphics Port Interface Specification, Revision 3.0 http://www.agpforum.org/
Low Pin Count Interface Specification, Revision 1.0
http://developer.intel.com/
design/chipsets/industry/
lpc.htm
PCI Local Bus Specification, Revision 2.2 http://www.pcisig.com/
PCI-PCI Bridge Specification, Revision 1.0 http://www.pcisig.com/
PCI Bus Power Management Interface Specification, Revision 1.0 http://www.pcisig.com/
Universal Serial Bus 2.0 Specification http://www.usb.org/
Advance Configuration and Power Interface (ACPI) Specification http://www.teleport.com/~acpi/
Term Description
MCH
The Memory Controller Hub component contains the processor interface and system
memory interface. The MCH communicates with the I/O Controller Hub 4 (ICH4) and
other controller hubs over a proprietary interconnect called the Hub Interface.