Hub Datasheet

128 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.8.11 SBUSN2—Secondary Bus Number Register (D2:F0)
Address Offset: 19h
Default Value: 00h
Attribute: R/W
Size: 8 bits
This register identifies the bus number assigned to the second bus side of the virtual PCI-to-PCI
bridge (the HI_B connection). This number is programmed by the PCI configuration software to
allow mapping of configuration cycles to a second bridge device connected to HI_B.
3.8.12 SUBUSN2—Subordinate Bus Number Register (D2:F0)
Address Offset: 1Ah
Default Value: 00h
Attribute: R/W
Size: 8 bits
This register identifies the subordinate bus (if any) that resides at the level below the secondary hub
interface. This number is programmed by the PCI configuration software to allow mapping of
configuration cycles to devices subordinate to the secondary hub interface port.
Bits
Default,
Access
Description
7:0
00h
R/W
Secondary Bus Number (BUSN). This field is programmed by configuration software
with the lowest bus number of the busses connected to HI_B. Since both bus 0, device 2
and the PCI-to-PCI bridge on the other end of the hub interface are considered by
configuration software to be PCI bridges, this bus number will always correspond to the
bus number assigned to HI_B.
Bits
Default,
Access
Description
7:0
00h
R/W
Subordinate Bus Number (BUSN). This register is programmed by configuration
software with the number of the highest subordinate bus that lies behind the device 2
bridge.