Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 113
Register Description
3.7.23 BCTRL1—Bridge Control Register (D1:F0)
Address Offset: 3Eh
Default Value: 00h
Attribute: R/W, RO
Size: 8 bits
This register provides extensions to the PCICMD1 register that are specific to PCI-to-PCI bridges.
The BCTRL provides additional control for the secondary interface (i.e., AGP) as well as some bits
that affect the overall behavior of the virtual PCI-to-PCI bridge embedded within MCH (e.g., VGA
compatible address ranges mapping).
Bits
Default,
Access
Description
7
0b
RO
Fast Back-to-Back Enable (FB2BEN). Hardwired to 0. The MCH does not generate
fast back-to-back cycles as a master on AGP.
6
0b
RO
Secondary Bus Reset (SRESET). Hardwired to 0. MCH does not support generation
of reset via this bit on the AGP.
5
0b
RO
Master Abort Mode (MAMODE). Hardwired to 0. When acting as a master on AGP,
the MCH will drop writes and return all 1s during reads when a Master Abort occurs.
4 Reserved
3
0b
R/W
VGA Enable (VGAEN). This bit, along with the MDAP bit in the MCHCFG register
(offset 50h), controls the routing of processor-initiated transactions targeting VGA
compatible I/O and memory address ranges. Note that only one of device 1–2’s
VGAEN bits are allowed to be set. This must be enforced via software.
2
0b
R/W
ISA Enable (ISAEN). This bit modifies the response by the MCH to an I/O access
issued by the processor that targets ISA I/O addresses. This applies only to I/O
addresses that are enabled by the IOBASE and IOLIMIT registers.
0 = Enable. All addresses defined by the IOBASE and IOLIMIT for processor I/O
transactions are mapped to AGP. (Default)
1 = Disable. MCH will not forward to AGP any I/O transactions addressing the last
768 bytes in each 1-KB block, even if the addresses are within the range defined
by the IOBASE and IOLIMIT registers. Instead of going to AGP, these cycles will
be forwarded to HI_A where they can be subtractively or positively claimed by the
ISA bridge.
1
0b
R/W
SERR Enable (SERREN). This bit controls forwarding SERR# on the secondary
interface to the primary interface.
0 = Disable.
1 = Enable. MCH generates SERR messages to HI_A when the SERR# pin on AGP/
PCI is asserted and when the messages are enabled by the SERRE bit in the
PCICMD1 register.
0
0b
R/W
Parity Error Response Enable (PEREN). This bit controls MCH’s response to data
phase parity errors on AGP. Other types of error conditions can still be signaled via
SERR messaging independent of this bit’s state.
0 = Disable. Address and data parity errors on AGP are not reported via the MCH
HI_A SERR messaging mechanism.
1 = Enable. G_PERR# is not implemented by the MCH. However, when this bit is set
to 1, address and data parity errors detected on AGP are reported via the HI_A
SERR messaging mechanism, if further enabled by SERRE1.
VGAEN MDAP Description
0 0 All References to MDA and VGA space are routed to HI_A
0 1 Illegal combination
10
All VGA references are routed to this bus. MDA references
are routed to HI_A
11
All VGA references are routed to this bus. MDA references
are routed to HI_A