Datasheet

Datasheet 209
Intel Manageability Engine Subsystem PCI (D3:F0,F3)
7.2.8 KTLCR—KT Line Control
B/D/F/Type: 0/3/3/KT MM/IO
Address Offset: 3h
Default Value: 03h
Access: RW
Size: 8 bits
The line control register specifies the format of the asynchronous data communications
exchange and sets the DLAB bit. Most bits in this register have no affect on hardware
and are only used by the FW.
Note: Reset: Host System Reset or D3->D0 transition.
Bit Access
Default
Value
Description
7RW0b
Divisor Latch Address Bit (DLAB): This bit is set when the Host wants to
read/write the Divisor Latch LSB and MSB Registers. This bit is cleared when the
Host wants to access the Receive Buffer Register or the Transmit Holding
Register or the Interrupt Enable Register.
6RW0bBreak Control (BC): This bit has no affect on hardware.
5:4 RW 00b Parity Bit Mode (PBM): This bit has no affect on hardware.
3RW0bParity Enable (PE): This bit has no affect on hardware.
2RW0bStop Bit Select (SBS): This bit has no affect on hardware.
1:0 RW 11b Word Select Byte (WSB): This bit has no affect on hardware.