Datasheet

Datasheet 123
DRAM Controller Registers (D0:F0)
5.2.31 EPC0DRB0—EP Channel 0 DRAM Rank Boundary Address 0
B/D/F/Type: 0/0/0/MCHBAR
Address Offset: A00–A01h
Default Value: 0000h
Access: RW, RO
Size: 16 bits
5.2.32 EPC0DRB1—EP Channel 0 DRAM Rank Boundary Address 1
B/D/F/Type: 0/0/0/MCHBAR
Address Offset: A02–A03h
Default Value: 0000h
Access: RW, RO
Size: 16 bits
See C0DRB0 register.
5.2.33 EPC0DRB2—EP Channel 0 DRAM Rank Boundary Address 2
B/D/F/Type: 0/0/0/MCHBAR
Address Offset: A04–A05h
Default Value: 0000h
Access: RW, RO
Size: 16 bits
See C0DRB0 register.
Bit Access
Default
Value
Description
15:10 RO 000000b Reserved
9:0 RW 000h Channel 0 Dram Rank Boundary Address 0 (C0DRBA0):
Bit Access
Default
Value
Description
15:10 RO 000000b Reserved
9:0 RW 000h Channel 0 Dram Rank Boundary Address 1 (C0DRBA1):
Bit Access
Default
Value
Description
15:10 RO 000000b Reserved
9:0 RW 000h Channel 0 DRAM Rank Boundary Address 2 (C0DRBA2):