Vol 1

Electrical Specifications
96 Intel® Xeon® Product 2800/4800/8800 v2 Product Family
Datasheet Volume One, February 2014
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. VCLK is VMSE{0/1/2/3}_CLK_DN/DP[3:0].
3. Maximum High pulse width is constant High when there are no MEM_HOT_C{01/23}_N events, and the MH_SENSE_EN=0.
4. MH_SENSE_PERIOD is the MEM_HOT_C{01/23}_N sense period and guarantees external assertion detection, see Intel®
Xeon® Processor E7-2800/4800/8800 v2 Product Family Datasheet - Volume Two: Functional Description for details. This is
the configurable sense period and sense assertion time. When sense assertion time is set to zero, and the processor is
asserting MEM_HOT_C{01/23}_N it will ignore externally asserted MEM_HOT_C{01/23}_N.
a. Sense period: 50 uS, 100 uS, 200 uS, or 400 uS.
b. Sense assertion time: 0, 1 uS, 1.5 uS, 2 uS, 2.5 uS, 3 uS, or 3.5 uS
5. T
pwrgood_fall
and T
pwrgood_rise
are measured 0.3*VTT to 0.7*VTT.
6. These signals are sampled after PWRGOOD assertion.
7. To meet TSC (Time Stamp Counter) multi-socket sampling, PWRGOOD must arrive to all processors within 1 BCLK{0/1} and
the BCLK{0/1} skew between the sockets should be less than one-half (1/2) BCLK{0/1} cycle.
8. If EAR_N is used in the design, this signal requires a minimum of 100 us delay from PWRGOOD assertion.
6.10.1.1 PCI Express AC Specifications
Intel® Xeon® E7 v2 processor AC specifications for the PCI Express* are available in
the PCI Express® Base Specification - Revision 3.0. This document will provide only the
processor exceptions to the PCI Express® Base Specification - Revision 3.0.
T9: FRB Warm Boot: RESET_N de-assertion to
PROCHOT_N de-assertion
1uS6-21
T2: PMSYNC Input Pulse Width Low 4 BCLK0 6-18
T1: PMSYNC Input Pulse Width High 4 68 BCLK0 6-18
T2: CAT_ERR_N Input Pulse Width Low 2 BCLK0 6-18 6
T1: CAT_ERR_N Input Pulse Width High 1 BCLK0 6-18
T2: CAT_ERR_N Output Pulse Width Low 16 BCLK0 6-18
T1: CAT_ERR_N Output Pulse Width High 1 BCLK0 6-18
T2: CPU_ONLY_RESET Output Pulse Width Low 479 BCLK0 6-18
T1: CPU_ONLY_RESET Output Pulse Width High 479 BCLK0 6-18
T10: THERMTRIP_N assertion until V
CC
/V
TT
/V
VMSE
/V
SA
/V
CCPLL
removed
500 ms 6-24 6
MEM_HOT_C{01/23}_N Output Pulse Width Low
and High
1VCLK2,3
MEM_HOT_C{01/23}_N Input Pulse Width Low >MH_SENSE
_PERIOD
<=MH_SENSE_
PERIOD
uS 6-23 4
T3:PWRGOOD Input Signals Rise Time
T4:PWRGOOD Input Signals Fall Time
20 ns 6-18 5
T11: BCLK0 stable to PWRGOOD assertion 10 BCLK0 6-22
T12: PWRGOOD assertion to RESET_N de-assertion 5.0 100 ms 6-22 7, 8
V
CCPLL
stable to PWRGOOD assertion 1 ms 6-22
T13: T
Setup:
Power-On Configuration Setup Time to
PWRGOOD assertion, Signals: BMCINIT,
TXT_PLTEN, FRMAGENT, TXT_AGENT,
SAFE_MODE_BOOT, SOCKET_ID[1:0]
1uS6-22 6
T14: T
Hold:
Power-On Configuration Hold Time,
Signals: BMCINIT, TXT_PLTEN, FRMAGENT,
TXT_AGENT, SAFE_MODE_BOOT, SOCKET_ID[1:0]
uS 6-22 6
T18: VSA Assertion to PWRGOOD Assertion 2 ms 6-22
Table 6-28. Processor Asynchronous Sideband and Miscellaneous Signals AC
Specifications (Sheet 2 of 2)
Parameter Min Max Unit Figure Notes
1
∞