Vol 1

Overview
14 Intel® Xeon® Processor E7-8800/4800/2800 v2 Product Family
Datasheet Volume One, February 2014
• Intel® Advanced Vector Extensions (Intel® AVX)
• Intel® Hyper-Threading Technology
• Execute Disable Bit
• Intel® Turbo Boost Technology
• Intel® Intelligent Power Technology
• Enhanced Intel SpeedStep® Technology
1.2 Interfaces
1.2.1 System Memory Support
• Intel® Xeon® E7 v2 processor supports 4 Intel
®
SMI Gen2 channels
• Registered DDR3 DIMMs
• LR DIMM (Load Reduced DIMM) for buffered memory solutions demanding higher
capacity memory subsystems
• Independent channel mode or lockstep mode
• Data burst length of eight cycles for independent channel mode and burst length of
4 cycles for lockstep mode
• Memory DDR3 data transfer rates of 1066, 1333, and 1600 MT/s
• 64-bit wide channels plus 8-bits of ECC support for each channel
• DDR3 standard I/O Voltage of 1.5 V and DDR3 Low Voltage of 1.35 V
• 2-GB, 4-GB and 8-GB DDR3 DRAM technologies supported
• Up to 24 DIMMs supported per socket
• RAS Support (including and not limited to):
— Rank Level Sparing
— Demand and Patrol Scrubbing
— DRAM Single Device Data Correction (SDDC) for any single x4 or x8 DRAM
device failure in lock step mode, and x4 in independent mode
— Lockstep mode where channels 0 & 1 and channels 2 & 3 are operated in
lockstep mode
— The combination of rank sparing and memory mirroring is not supported
— Data scrambling with address to ease detection of write errors to an incorrect
address
— Error reporting via Machine Check Architecture
— Read Retry during CRC error handling checks by iMC
— Channel mirroring within a memory controller on a socket
— Channel Mirroring mode is supported on memory channels 0 & 1 and channels
2 & 3
— Error Containment Recovery
• Improved Thermal Throttling with dynamic Closed Loop Thermal Throttling (CLTT)
• Memory thermal monitoring support for DIMM temperature via two memory pins,
MEM_HOT_C{01/23}_N