Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 63
Register Description
5:4
01b
R/W
CAS# Latency (t
CL
). The number of clocks between the rising edge used by DRAM to
sample the Read Command and the rising edge that is used by the DRAM to drive read
data.
00 = 2.5
01 = 2
10 = Reserved
11 = Reserved
3
0b
R/W
Write RAS# to CAS# Delay (t
RCD
). This bit controls the number of clocks inserted
between a row activate command and a write command to that row.
0 = 3 DRAM Clocks
1 = 2 DRAM Clocks
2:1
00b
R/W
READ RAS# to CAS# Delay (t
RCD
). This bit controls the number of clocks inserted
between a row activate command and a read command to that row.
00 = 5 DRAM clocks
01 = 4 DRAM clocks
10 = 3 DRAM clocks
11 = 2 DRAM clocks
Note that t
RCD
is first expanded (beyond 2,3 clocks options), to correctly support
t
RAS-min
timing during auto-precharge cycles. Also, note that t
RCD
is separated between
reads and writes, since slower timing (with auto-precharge) is needed for read cycles
only. The following tables should be used by BIOS to correctly set t
RCD
, based on DDR-
SDRAM speed, CAS Latency, and whether auto-precharge is enabled for read cycles.
Case 1: DDR200, t
RAS
= 5 clocks (50 ns).
Without AP With AP
RD-RCD 2 3
WR-RCD 2 2
Case 2: DDR266, t
RAS
= 6 clocks (45 ns).
Without AP With AP
RD-RCD 3 4
WR-RCD 3 3
0
0b
R/W
DRAM RAS# Precharge (t
RP
). This bit controls the number of clocks that are inserted
between a row precharge command and an activate command to the same row.
0 = 3 DRAM clocks
1 = 2 DRAM clocks
Bits
Default,
Access
Description