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Intel

E7505 Chipset MCH Datasheet 39

This chapter describes the MCH PCI configuration registers. A detailed register bit description is

provided. The MCH contains two sets of software accessible registers, accessed via the Host

processor I/O address space:

• Control registers – These registers are I/O mapped into the processor I/O space, which

control access to PCI configuration space (see section entitled I/O Mapped Registers)

• Internal configuration registers – These registers, which reside within the MCH, are

partitioned into multiple logical device register sets (“logical” since they reside within a single

physical device). There are three primary device register sets; for the DRAM controller/HI_A

(controls PCI_A, i.e., DRAM configuration, other chipset operating parameters, and optional

features); another set is for the AGP; and another set for the HI_B interface.

The MCH supports PCI configuration space accesses using the mechanism denoted as

Configuration Mechanism #1 in the PCI specification.

The MCH internal registers (I/O mapped and configuration registers) are accessible by the host.

The registers can be accessed as Byte (8-bit), Word (16-bit), or DWord (32-bit) quantities, with the

exception of the CONFIG_ADDRESS Register, which can only be accessed as a DWord. All

multi-byte numeric fields use “little-endian” ordering (i.e., lower addresses contain the least

significant parts of the field).

3.1 Register Nomenclature and Access Attributes

Term Description

RO Read-Only. If a register is read-only, writes to this register have no effect.

R/W Read/Write. A register with this attribute can be read and written

R/WC

Read/Write Clear. A register bit with this attribute can be read and written. However, a write

of a 1 clears (sets to 0) the corresponding bit and a write of a 0 has no effect.

R/WO

Read/Write-Once. A register bit with this attribute can be written to only once after power up.

After the first write, the bit becomes read-only.

R/W/L Read/Write/Lock. A register with this attribute can be read, written, and locked.

L Lock. A register bit with this attribute becomes read only after a lock bit is set.

Sticky

Certain registers in the MCH are sticky through a soft-reset. They will only be reset on a hard

reset or power-good reset. These registers in general are the error logging registers and a

few special cases.

Reserved Bits

Some of the MCH registers described in this section contain reserved bits. These bits are

labeled “Reserved” or “Intel Reserved.” Software must deal correctly with fields that are

reserved. On reads, software must use appropriate masks to extract the defined bits and not

rely on reserved bits being any particular value. On writes, software must ensure that the

values of reserved bit positions are preserved. That is, the values of reserved bit positions

must first be read, merged with the new values for other bit positions and then written back.

Note that software does not need to perform read, merge, write operation for the

configuration address register.