Hub Datasheet

Signal Description
30 Intel
®
E7505 Chipset MCH Datasheet
CMDCLK_B[7:0]#
O
CMOS
Differential Clock: Output to DIMMs. Commands are referenced to the
rising edge of CMDCLK_x and the falling edge of CMDCLK_x#. One per
DIMM for registered DIMMs, three per DIMM for unbuffered DIMMs.
• CMDCLK_B6# is multiplexed with CS_B4#
CS_B[5:0]#
O
SSTL-2
Chip Select: The chip select inputs determine which row a command is
targeting. There is one per row (two per DIMM).
Muxed Chip Selects and clocks. These signals are chip select outputs on
a 3-DIMM motherboard supporting registered DIMMs only, and clock
outputs on a 2-DIMM motherboard that supports unbuffered or registered
DIMMs. A configuration bit determines their function. The default function is
chip selects.
• CK2/CK2# are at pins 76 and 75 of the DIMM.
MA_B[13:0]
O
SSTL-2
Memory Address: These signals provide the row address for Active
commands, and the column address and auto-precharge bit for read/write
commands, to select one location out of the memory array in the respective
bank. MA_B10 is sampled during a precharge command to determine
whether the precharge applies to one bank (MA_B10 low) or all banks
(MA_B10 high). If only one bank is to be precharged, the bank is selected by
BA_B0, BA_B1. The address inputs also provide the op–code during a
Mode Register Set command. BA_B0 and BA_B1 define which mode
register is loaded during the Mode Register Set command (MRS or EMRS).
BA_B[1:0]
O
SSTL-2
Bank Address: The Bank Address specifies which bank an activate, read,
write, or precharge command is targeting.
RAS_B#
O
SSTL-2
Row Address Strobe: This signal is used to indicate an activate command,
opening a page specified by the MA_x signals in the bank specified by the
BA_x signals. It is used with WE_B# to indicate a precharge command,
closing the page in the bank specified by the BA_x signals. RAS_B# is also
used to enter register set mode or start an auto refresh or enter self refresh.
Table 2-3. DDR Channel B Signals (Sheet 2 of 3)
Signal Name Type Description
Signal 2 DIMM 3 DIMM
CMDCLK_B7# DIMM 1 CK2#
CMDCLK_B6#/CS_B4# DIMM 0 CK2#
CMDCLK_B5# DIMM 1 CK1#
CMDCLK_B4# DIMM 0 CK1#
CMDCLK_B3#
CMDCLK_B2# DIMM 2 CK0#
CMDCLK_B1# DIMM 1 CK0# DIMM 1 CK0#
CMDCLK_B0# DIMM 0 CK0# DIMM 0 CK0#
Signal 2 DIMM 3 DIMM
CS_B5#/CMDCLK_B6 DIMM 2 S1#
CS_B4#/CMDCLK_B6# DIMM 2 S0#
CS_B3# DIMM 1 S1# DIMM 1 S1#
CS_B2# DIMM 1 S0# DIMM 1 S0#
CS_B1# DIMM 0 S1# DIMM 0 S1#
CS_B0# DIMM 0 S0# DIMM 0 S0#