Hub Datasheet

142 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.9.14 SMICMD2—SMI Command Register (D2:F1)
Address Offset: A2h
Default Value: 00h
Sticky No
Attribute: RO, R/W
Size: 8 bits
This register determines whether SMI will be generated when the associated flag is set in FERR or
NERR. When an error flag is set in the FERR or NERR Register, it can generate an SERR, SMI, or
SCI when enabled in the SERRCMD, SMICMD, or SCICMD Registers, respectively. Only one
message type can be enabled.
Bits
Default,
Access
Description
7 Reserved
6
R/W
0b
SMI on MCH Received SERR from HI_B Enable.
0 = No SMI generation
1 = Generate SMI if bit 6 is set in HIB_FERR or HIB_NERR
5
R/W
0b
SMI on MCH Master Abort to a HI_B Request Enable.
0 = No SMI generation
1 = Generate SMI if bit 5 is set in HIB_FERR or HIB_NERR
4
R/W
0b
SMI on Received Target Abort on HI_B Enable.
0 = No SMI generation
1 = Generate SERR if bit 4 is set in HIB_FERR or HIB_NERR
3
R/W
0b
SMI on Correctable Error on Header/Address from HI_B Enable.
0 = No SMI generation
1 = Generate SMI if bit 3 is set in HIB_FERR or HIB_NERR
2
R/W
0b
SMI on Correctable Error on Data from HI_B Enable.
0 = No SMI generation
1 = Generate SMI if bit 2 is set in HIB_FERR or HIB_NERR
1
R/W
0b
SMI on Uncorrectable Error on Header/Address from HI_B Enable.
0 = No SMI generation
1 = Generate SMI if bit 1is set in HIB_FERR or HIB_NERR
0
R/W
0b
SMI on Uncorrectable Error on Data Transfer from HI_B Enable.
0 = No SMI generation
1 = Generate SMI if bit 0 is set in HIB_FERR or HIB_NERR