Hub Datasheet

136 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.9.3 PCICMD—PCI Command Register (D2:F1)
Address Offset: 04–05h
Default Value: 0000h
Sticky No
Attribute: RO, R/W
Size: 16 bits
3.9.4 PCISTS—PCI Status Register (D2:F1)
Address Offset: 06–07h
Default Value: 0000h
Sticky No
Attribute: RO, R/WC
Size: 16 bits
Bits
Default,
Access
Description
15:9 Reserved
8
0b
R/W
SERR Enable (SERRE). This bit is a global enable bit for Device 2 SERR messaging.
The MCH does not have an SERR# signal. The MCH communicates the SERR
condition by sending an SERR message over HI_A to the Intel
®
ICH4.
0 = Disable. SERR message is not generated by the MCH for Device 2
1 = Enable. MCH is enabled to generate SERR messages over HI_A for specific
Device 2 error conditions that are individually enabled in the SERRCMD2
register. The error status is reported in the FERR/NERR and PCISTS registers.
7:0 Reserved
Bits
Default,
Access
Description
15 Reserved
14
0b
R/WC
Signaled System Error (SSE). Software sets this bit to 0 by writing a 1 to it.
0 = MCH Device 2 Did Not generate SERR message over HI-A.
1 = MCH Device 2 generated an SERR message over HI_A for any enabled Device 2
error condition. Device 2 error conditions are enabled in the PCICMD and
SERRCMD2 registers. Device 2 error flags are read/reset from the PCISTS or
FERR/NERR registers.
13:0 Reserved