Hub Datasheet

132 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.8.18 PMBASE2—Prefetchable Memory Base Address Register
(D2:F0)
Address Offset: 24–25h
Default Value: FFF0h
Attribute: R/W, RO
Size: 16 bits
This register controls the processor-to-HI_B prefetchable memory accesses. The upper 12 bits of
the register are read/write and correspond to the upper 12 address bits A31:20 of the 36-bit address.
For the purpose of address decode, bits A19:0 are assumed to be 0. Thus, the bottom of the defined
memory address range will be aligned to a 1-MB boundary.
3.8.19 PMLIMIT2—Prefetchable Memory Limit Address Register
(D2:F0)
Address Offset: 26–27h
Default Value: 0000h
Attribute: R/W, RO
Size: 16 bits
This register controls the processor-to-HI_B prefetchable memory accesses. The upper 12 bits of
the register are read/write and correspond to the upper 12 address bits A31:20 of the 36-bit address.
For the purpose of address decode, bits A19:0 are assumed to be FFFFh. Thus, the top of the
defined memory address range will be at the top of a 1-MB aligned memory block.
Bits
Default,
Access
Description
15:4
FFFh
R/W
Prefetchable Memory Address Base (PMBASE). These bits corresponds to A31:20 of
the lower limit of the address range passed by bridge device 2 across HI_B.
3:0 Reserved. Hardwired to 0h. The MCH does not support Out Bound 64-bit addressing.
Bits
Default,
Access
Description
15:4
000h
R/W
Prefetchable Memory Address Limit (PMLIMIT). These bits corresponds to A31:20 of
the upper limit of the address range passed by bridge device 2 across HI_B
3:0 Reserved. Hardwired to 0h. The MCH does not support Out Bound 64-bit addressing.