Hub Datasheet

104 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.7.10 APBASELO—AGP Aperture Base Address Register (D1:F0)
Address Offset: 10–13h
Default Value: 0000 0008h
Attribute: R/W, RO
Size: 32 bits
Note that the intention is that the APSIZE register force individual bits to Read Only as 0, although
the E7505 (and other chips) implementation only causes them to be Read Only, and does not force
them to 0. The default is 0, so the difference would only occur if the aperture was set to a small
size, specific APBASE bits were set to ones, and the aperture size was then increased. APBASE
bits affected by the APSIZE change would then be Read Only as whatever value they had
previously been written. While this could cause bits to read back as 1 instead of 0, the actual
aperture decode will be done properly according to the APSIZE register. Software can avoid this
situation by writing the APBASE register to 0 prior to increasing the aperture size via APSIZE.
The aperture should be disabled prior to any change in APBASE or APSIZE. Set by BIOS.
Bits
Default,
Access
Description
31:28
0h
R/W
Upper Programmable Base Address (UPBITS). These bits are part of the
aperture base set by configuration software to locate the base address of the
graphics aperture. They correspond to bits 31:28 of the base address in the
processor's address space that will cause a graphics aperture translation to be
inserted into the path of any memory read or write.
27:22
00h
R/W
or
RO
depending
on aperture
size
Middle Hardwired/Programmable Base Address (MIDBITS). These bits are part
of the aperture base set by configuration software to locate the base address of the
graphics aperture. They correspond to bits 27:4 of the base address in the
processor's address space that will cause a graphics aperture translation to be
inserted into the path of any memory read or write. These bits can individually
behave as read only if programmed to do so by the APSIZE bits of the APSIZE
register. This will cause configuration software to understand that the granularity of
the graphics aperture base address is either finer or more coarse, depending on the
bits set by MCH-specific configuration software in APSIZE.
NOTE: Not forced to 0 when read only.
21:4
00000h
RO
Hardwired to 0s. This forces minimum AGP aperture size to be 4 MB or greater.
3
1b
RO
Prefetchable. Hardwired to 1. This identifies the Graphics AGP aperture range as
prefetchable (i.e., there are no side effects on reads, the device returns all bytes on
reads regardless of the byte enables, and Core-logic may merge host processor
writes into this range without causing errors).
2:1
“00”b
RO
Type. Hardwired to 00. The AGP allows the target to support a 32-bit Base Address
register for APBASE.
00 = 32-bit Base Address register; NGP aperture can be located anywhere within a
32-bit address space
0
0b
RO
Memory. Hardwired to 0. This indicates that the Graphics AGP aperture must reside
in “Memory” space – as defined by the PCI specification.