Datasheet

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel
®
3210 MCH only)
236 Datasheet
8.31 MA—Message Address
B/D/F/Type: 0/6/0/PCI
Address Offset: 94–97h
Default Value: 00000000h
Access: RO, RW
Size: 32 bits
8.32 MD—Message Data
B/D/F/Type: 0/6/0/PCI
Address Offset: 98–99h
Default Value: 0000h
Access: RW
Size: 16 bits
8.33 PE_CAPL—PCI Express* Capability List
B/D/F/Type: 0/6/0/PCI
Address Offset: A0–A1h
Default Value: 0010h
Access: RO
Size: 16 bits
This register enumerates the PCI Express capability structure.
Bit Access
Default
Value
Description
31:2 RW
0000000
0h
Message Address (MA): Used by system software to assign an MSI address to
the device. The device handles an MSI by writing the padded contents of the MD
register to this address.
1:0 RO 00b
Force DWord Align (FDWA): Hardwired to 0 so that addresses assigned by
system software are always aligned on a DWord address boundary.
Bit Access
Default
Value
Description
15:0 RW 0000h
Message Data (MD): Base message data pattern assigned by system software
and used to handle an MSI from the device.
When the device must generate an interrupt request, it writes a 32-bit value to
the memory address specified in the MA register. The upper 16-bits are always
set to 0. The lower 16-bits are supplied by this register.
Bit Access
Default
Value
Description
15:8 RO 00h
Pointer to Next Capability (PNC): This value terminates the capabilities list.
The Virtual Channel capability and any other PCI Express specific capabilities
that are reported via this mechanism are in a separate capabilities list located
entirely within PCI Express Extended Configuration Space.
7:0 RO 10h
Capability ID (CID): Identifies this linked list item (capability structure) as
being for PCI Express registers.