Datasheet

DRAM Controller Registers (D0:F0)
108 Datasheet
5.2.11 C0CYCTRKRD—Channel 0 CYCTRK READ
B/D/F/Type: 0/0/0/MCHBAR
Address Offset: 258–25Ah
Default Value: 000000h
Access: RO, RW
Size: 24 bits
Channel 0 CYCTRK RD registers.
5.2.12 C0CYCTRKREFR—Channel 0 CYCTRK REFR
B/D/F/Type: 0/0/0/MCHBAR
Address Offset: 25B–25Ch
Default Value: 0000h
Access: RO, RW
Size: 16 bits
Channel 0 CYCTRK Refresh registers.
Bit Access
Default
Value
Description
23:21 RO 000b Reserved
20:17 RW 0h
Min ACT To READ Delayed (C0sd_cr_act_rd): This field indicates the
minimum allowed spacing (in DRAM clocks) between the ACT and READ
commands to the same rank-bank. This field corresponds to t
RCD_rd
in the DDR
specification.
16:12 RW 00000b
Same Rank Write To READ Delayed (C0sd_cr_wrsr_rd): This field indicates
the minimum allowed spacing (in DRAM clocks) between the WRITE and READ
commands to the same rank. This field corresponds to t
WTR
in the DDR
specification.
11:8 RW 0000b
Different Ranks Write To READ Delayed (C0sd_cr_wrdr_rd): This field
indicates the minimum allowed spacing (in DRAM clocks) between the WRITE
and READ commands to different ranks. This field corresponds to t
WR_RD
in the
DDR specification.
7:4 RW 0000b
Same Rank Read To Read Delayed (C0sd_cr_rdsr_rd): This field indicates
the minimum allowed spacing (in DRAM clocks) between two READ commands to
the same rank.
3:0 RW 0000b
Different Ranks Read To Read Delayed (C0sd_cr_rddr_rd): This field
indicates the minimum allowed spacing (in DRAM clocks) between two READ
commands to different ranks. This field corresponds to t
RD_RD
.
Bit Access
Default
Value
Description
15:13 RO 000b Reserved
12:9 RW 0000b
Same Rank PALL to REF Delayed (C0sd_cr_pchgall_rfsh): This field
indicates the minimum allowed spacing (in DRAM clocks) between the PRE-ALL
and REF commands to the same rank.
8:0 RW
0000000
00b
Same Rank REF to REF Delayed (C0sd_cr_rfsh_rfsh): This field indicates
the minimum allowed spacing (in DRAM clocks) between two REF commands to
same ranks.