Specification Update

Intel
®
Xeon
®
Processor 7000 Series 39
Specification Update, March 2010
Workaround: Software should ensure that “host address-space size” VM exit control has the same
value as IA32_EFER.LMA at the time of VMLAUNCH/VMRESUME.
Status: For the steppings affected, see the Summary Table of Changes.
A80. VMCALL to activate dual-monitor treatment of SMIS and SMM ignores
reserved bit settings in VM-exit control field
Problem: Processors supporting Intel® Virtualization Technology can execute VMCALL from
within the Virtual Machine Monitor (VMM) to activate dual-monitor treatment of SMIs
and SMM. Due to this erratum, if reserved bits are set to values inconsistent with VMX
Capability MSRs, VMCALL may not VMFail.
Implication: VMCALL executed to activate dual-monitor treatment of SMIs and SMM may not VMFail
due to incorrect reserved bit settings in VM-Exit control field.
Workaround: Software should ensure that all VMCS reserved bits are set to values consistent with
VMX Capability MSRs.
Status: For the steppings affected, see the Summary Table of Changes.
A81. Using 2M/4M pages when A20M# is asserted may result in incorrect
address translations
Problem: An external A20M# pin if enabled forces address bit 20 to be masked (forced to zero)
to emulate real-address mode address wraparound at 1 MB. However, if all of the
following conditions are met, address bit 20 may not be masked.
• Paging is enabled .
• A linear address has bit 20 set.
• The address references a large page.
• A20M# is enabled.
Implication: When A20M# is enabled and an address references a large page, the resulting
translated physical address may be incorrect. This erratum has not been observed with
any commercially available operating system.
Workaround: Operating systems should not allow A20M# to be enabled if the masking of address bit
20 could be applied to an address that references a large page. A20M# is normally
only used with the first megabyte of memory.
Status: For the steppings affected, see the Summary Table of Changes.
A82. Writing shared unaligned data that crosses a cache line without
proper semaphores or barriers may expose a memory ordering issue
Problem: Software which is written so that multiple agents can modify the same shared
unaligned memory location at the same time may experience a memory ordering issue
if multiple loads access this shared data shortly thereafter. Exposure to this problem
requires the use of a data write which spans a cache line boundary.
Implication: This erratum may cause loads to be observed out of order. Intel has not observed this
erratum with any commercially available software or system.
Workaround: Software should ensure at least one of the following is true when modifying shared
data by multiple agents:
• The shared data is aligned
• Proper semaphores or barriers are used in order to prevent concurrent data
accesses.
Status: For the steppings affected, see the Summary Table of Changes.