Specification Update

14 Intel
®
E7320 Memory Controller Hub (MCH) Specification Update
Errata
Express specification requires that the link attempt to train as a x1 on lane 0 - the MCH will not
train in this scenario.
Failures are anticipated to occur because of a broken transmitter/receiver path, or a silent
transmitter. None of those failure modes will cause the MCH to fail to train, since either the
receiver termination will be missing, or the transmitted signals will not be seen at the MCH. In
order to see invalid transmitted signals at the MCH, either a logic bug in the other PCI Express
endpoint would be required, or a signal integrity issue so severe as to make operation impossible.
Workaround: None
Status: For the steppings effected, see the Summary Table of Changes.
17. DIMM sparing issue with demand scrub enabled
Problem: When spare copy is in progress and a demand scrub (as a result of a demand fetch with a
correctable error) to an address resolving to the SCRUBLIM is performed, the process of spare
copy from the failing DIMM to spare DIMM may terminate prematurely.
Implication: A system hang may occur when the spare DIMM is brought “on-line” prematurely and bad data is
read from this DIMM. This condition is a result of the premature exit of the spare copy process.
Workaround: BIOS should disable demand scrub prior to initiating spare copy and re-enable it after the data
migration is complete. Demand scrubbing can be enabled and disabled by updating the Scrub Limit
and Control Register (SCRUBLIM Device 8, Function 0, Offset C8-CBh bit 27).
Status: For the steppings effected, see the Summary Table of Changes.
18. Configuration transaction may be ignored in MCH when Configuration
Request Retry Status is enabled in PCI Express to PCI/PCI-X bridges
Problem: Under certain circumstances that include a mix of PCI Express traffic in the presence of
completions with Configuration Retry Status (configuration space traffic receiving CRS, and other
traffic that is posted / governed by Posted Flow Control credits) on a given PCI Express port, the
MCH may ignore and fail to issue an outbound configuration space access indefinitely. This
behavior has been observed in configurations with PCI Express to PCI/PCI-X bridge devices under
circumstances where at least one device “behind” the bridge is active and operational, while at least
one other device “behind” the bridge remains unresponsive to configuration requests for an
extended period of time. Such failures ultimately manifest themselves as CPU IERR# assertions,
which commonly precipitates a platform reboot. Completions with Configuration Request Retry
Status are generally sent by a PCI Express to PCI/PCI-X bridge when it relays configuration space
traffic to a PCI/PCI-X device which exhibits a long latency in responding to configuration space
traffic. The CRS completion status mechanism is intended to prevent a PCI Express completion
timeout from occurring in cases where historical PCI/PCI-X implementations would experience an
extended latency without response, but would not generate any timeout or associated error.
Implication: A system hang may occur.
Workaround: To avoid configuration transactions from being ignored, Intel strongly recommends that BIOS
should disable Configuration Request Retries in all PCI Express bridge devices. For Intel®
6700PXH 64-bit PCI Hub this is accomplished by clearing the Bridge Configuration Retry Enable
bit in the Device Control register (D0:F0,2:R04Ch bit 15). This bit is cleared by default. Some PCI
or PCI-X devices may require lengthy self-initialization sequence (up to 1.5 sec as defined by PCI
Express Base Specification 1.0a) to complete before they are able to service Configuration
Requests after reset. In order to ensure the ability of the system to successfully enumerate PCI
devices, BIOS should disable PCI Express Completion Timeout in the root port configuration of
MCH links connected to Intel® 6700PXH 64-bit PCI Hub, Intel® IOP332, and Intel® 41210
devices (including add-in cards) by setting the Completion Timeout Timer Disable bit in the
Vendor Specific command register (D2-3:F0:R045h bit 3). BIOS should ensure that the
Completion Timeout Timer remains enabled (default) for other active PCI Express links. BIOS