Datasheet

Electrical Specifications
Dual-Core Intel
®
Xeon
®
Processor 7000 Series Datasheet 21
2.5 Front Side Bus Signal Groups
The FSB signals are grouped by buffer type as listed in Table 2-4. The buffer type indicates which
AC and DC specifications apply to the signals. AGTL+ input signals have differential input buffers
that use GTLREF as a reference level. In this document, the term “AGTL+ Input” refers to the
AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output”
refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.
Implementing a source synchronous data bus requires specifying two sets of timing parameters.
One set is for common clock signals which are dependent upon the rising edge of BCLK0 (ADS#,
HIT#, HITM#, etc.). The second set is for the source synchronous signals that are relative to their
respective strobe lines (data and address) as well as the rising edge of BCLK0. Asynchronous
signals are present (A20M#, IGNNE#, etc.) and can become active at any time during the clock
cycle. Table 2-4 identifies signals as common clock, source synchronous, and asynchronous.
NOTES:
1. Refer to Section 5.1 for signal descriptions.
Table 2-4. Front Side Bus Pin Groups
Signal Group Type Signals
1
AGTL+ Common Clock Input Synchronous to BCLK[1:0] BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#,
TRDY#
AGTL+ Common Clock I/O Synchronous to BCLK[1:0] ADS#, AP[1:0]#, BINIT#, BNR#, BPM[5:0]#,
BR[3:0]#, DBSY#, DP[3:0]#, DRDY#, HIT#,
HITM#, LOCK#, MCERR#
AGTL+ Source Synchronous I/O Synchronous to associated
strobe
AGTL+ Strobe Input/Output Synchronous to BCLK[1:0] ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
AGTL+ Asynchronous Output Asynchronous FERR#/PBE#, IERR#, PROCHOT#,
GTL+ Asynchronous Input Asynchronous A20M#, FORCEPR#, IGNNE#, INIT#,
LINT0/INTR, LINT1/NMI, SMI#, STPCLK#
GTL+ Asynchronous Output Asynchronous THERMTRIP#
TAP Input Synchronous to TCK TCK, TDI, TMS
TAP Input Asynchronous TRST#
TAP Output Synchronous to TCK TDO
Front Side Bus Clock Input Clock BCLK[1:0]
SMBus Synchronous to SM_CLK SM_ALERT#, SM_CLK, SM_DAT,
SM_EP_A[2:0], SM_TS_A[1:0], SM_WP
Power/Other Power/Other BOOT_SELECT, BSEL[1:0], COMP0,
TESTHI[6:0], GTLREF[3:0], ODTEN,
PWRGOOD, RESERVED, SKTOCC#,
SLEW_CTRL, SM_VCC, TEST_BUS, V
CC
,
V
CCA
, V
CCIOPLL
, V
CCSENSE
, VID[5:0],
VIDPWRGD, V
SS
, V
SSA
, V
SSSENSE
, V
TT
,
VTTEN, PROCTYPE
Signals Associated Strobe
REQ[4:0]#,
A[37:36,16:3]#
ADSTB0#
A[39:38,35:17]# ADSTB1#
D[15:0]#, DBI0# DSTBP0#, DSTBN0#
D[31:16]#, DBI1# DSTBP1#, DSTBN1#
D[47:32]#, DBI2# DSTBP2#, DSTBN2#
D[63:48]#, DBI3# DSTBP3#, DSTBN3#