Vol 1

Intel® Xeon® Product 2800/4800/8800 v2 Product Family 63
Datasheet Volume One, February 2014
Signal Descriptions
5 Signal Descriptions
This chapter describes the Intel® Xeon® E7v2 processor signals. They are arranged in
functional groups according to their associated interface or category.
5.1 System Memory Interface
5.2 PCI Express Based Interface Signals
Note: PCI Express Ports 0 and 1 signals are receive and transmit differential pairs.
5.3 DMI2/PCI Express Port Signals
Table 5-1. Memory Channel Signals
Signal Name Description
MEM_SCL_C{3:0}
MEM_SDA_C{3:0}
SMBus clock for the dedicated interface to the serial presence
detect (SPD) and thermal sensors (TSoD) on the DIMMs.
VMSE{0/1/2/3}_CLK_N
VMSE{0/1/2/3}_CLK_P
Clocks to the memory buffer. This clock is used to capture the
VCMD# signals.
VMSE{0/1/2/3}_CMD[16:0] Command signals.
VMSE{0/1/2/3}_DQ[63:0] Data Bus. DDR3 Data bits.
VMSE{0/1/2/3}_DQS_P[8:0]
VMSE{0/1/2/3}_DQS_N[8:0]
Data strobes. Driven with edges in center of data, receive edges
are aligned with data edges.
VMSE{0/1/2/3}_ECC[7:0] Check bits. An error correction code is driven along with data on
these lines for DIMMs that support that capability
VMSE{0/1/2/3}_ERR_N Parity Error detected by Registered DIMM (one for each channel).
VMSE_PWR_OK Power good input signal used to indicate that the power supply is
stable for memory channels.
Table 5-2. PCI Express* Port Signals
Signal Name Description
PE{1:0}_RX_N[15:0]
PE{1:0}_RX_P[15:0]
PCIe Receive Data Input
PE{1:0}_TX_N[15:0]
PE{1:0}_TX_P[15:0]
PCIe Receive Data Output
Table 5-3. DMI2 to Port 0 Signals
Signal Name Description
DMI_RX_DN[3:0]
DMI_RX_DP[3:0]
DMI2 Receive Data Input
DMI_TX_DP[3:0]
DMI_TX_DN[3:0]
DMI2 Transmit Data Output