Vol 1

Intel® Xeon® Product 2800/4800/8800 v2 Product Family 175
Datasheet Volume One, February 2014
PIROM
9.3.3.2 RES3: Reserved 3
This locations are reserved. Writes to this register have no effect.
9.3.3.3 MP1CF: Maximum P1 Core Frequency
This location contains the maximum non-Turbo Boost core frequency for the processor.
The frequency should equate to the markings on the processor and/or the QDF/S-spec
speed even if the parts are not limited or locked to the intended speed. Format of this
field is in MHz, rounded to a whole number, and encoded in binary coded decimal.
Writes to this register have no effect.
Example: A 2.666 GHz processor will have a value of 2666h.
9.3.3.4 MP0CF: Maximum P0 Core Frequency
This location contains the maximum Turbo Boost core frequency for the processor. This
is the maximum intended speed for the part under any functional conditions. Format of
this field is in MHz, rounded to a whole number, and encoded in binary coded decimal.
Writes to this register have no effect.
Example: A processor with a maximum Turbo Boost frequency of 2.666 GHz will have
a value of 2666h.
Offset: 1Bh-1Ch
Bit Description
15:13 Reserved
00b-11b: Reserved
12:12 Processor Type
0b-1b: Processor Type
11:8 Processor Family
0h-Fh: Processor Family
7:4 Processor Model
0h-Fh: Processor Model
3:0 Processor Stepping
0h-Fh: Processor Stepping
Offset: 1Dh-1Eh
Bit Description
15:0 RESERVED
0000h-FFFFh: Reserved
Offset: 1F-20h
Bit Description
15:0 Maximum P1 Core Frequency
0000h-FFFFh: MHz