Vol 1

PIROM
174 Intel® Xeon® Product 2800/4800/8800 v2 Product Family
Datasheet Volume One, February 2014
9.3.2.4 SCS: System Clock Speed
This location contains the system clock frequency information. Systems may need to
read this offset to decide if all installed processors support the same system clock
speed. The data provided is the speed, rounded to a whole number, and reflected in
binary coded decimal. Writes to this register have no effect.
Example: A processor with system bus speed of 100 MHz will have a value of 0100h.
9.3.2.5 RES2: Reserved 2
This location is reserved. Writes to this register have no effect.
9.3.3 Processor Core Data
This section contains silicon-related data relevant to the processor cores.
9.3.3.1 CPUID: CPUID
This location contains the CPUID, Processor Type, Family, Model and Stepping. The
CPUID field is a copy of the results in EAX[15:0] from Function 1 of the CPUID
instruction. Writes to this register have no effect. Data format is hexidecimal.
Offset: 15h
Bit Description
7:2 Number of cores
1:0 Number of threads per core
Offset: 16h-17h
Bit Description
15:0 System Bus Speed
0000h-FFFFh: MHz
Offset: 18h-2Ah
Bit Description
23:0 RESERVED
000000h-FFFFFFh: Reserved