Vol 1

Intel® Xeon® Product 2800/4800/8800 v2 Product Family 105
Datasheet Volume One, February 2014
Electrical Specifications
11. If necessary, staggering of processor loads assumes all eternal rails to the processor in a node are powered
on together, and staggering occurs with the PWRGOOD signals. If the PWRGOOD signals are staggered,
then assertions of PWRGOOD must be at every 864 bclocks for Intel® Xeon® E7v2 and 384 bclocks for
later CPUs. There is no setup or hold requirement to the bclock.
12. <5ms
13. SVID driven by processor
14. For Intel® Xeon® E7v2, VCC is 0V until SVID drives data. For follow on CPUs, VCC is Vboot at ~1.7-1.8V.
Also, VCC comes up after VMSE_PWR_OK.
15. Platform (all CPUs) = 5 ms min and 500 ms max. For follow on CPUs, FIVR_FAULT may assert no sooner
than 1.8ms after CPU_PWRGOOD assertion. When FIVR_FAULT asserts, THERMTRIP_N will also assert.
16. When the CPU is held in reset, it uses ~10% of its TDP power.
17. BCLKs may be enabled before the processor gets any power.
18. BCLK needs to be stable 10 BLCKs minimum before CPU_PWRGOOD
19. BMCINIT, FRMAGENT, LEGACY_SKT, BIST_ENABLE, TXT_PLTEN, TXT_AGENT, SOCKET_ID[2:0]
20. 1us is the minimum set up time between power good straps and CPU_PWRGOOD
21. Hold until next power cycle
22. PROCHOT needs to be valid 0ns min
23. 100 BLCKs
24. PROCHOT# for socket disable sampling
25. The CPU warm reset requirement is 3.5ms minimum and 100ms maximum.
26. Power down requirements are as follows: For Intel® Xeon® E7v2 VCCPLL goes off first, followed by VSA
and VCC which can go down together. VTT(VCCIO_IN) are last. For follow on CPUs, VCCPLL goes off first,
followed by VCC_IN and then VTT.
27. Power up sequence is not to scale. Blue signals are Intel® Xeon® E7v2 specific. Green signals are specific
to later CPUs.
Figure 6-23. MEM_HOT_C{01/23}_N Event Assertion Waveform
sense output
select
MEM_HOT_N event assertion
sense output
select
sense sense sense sense
Sense period
Sense assertion time
MEM_HOT_N Event Start
MEM_HOT_N Event End