Specification Update

38 Intel
®
Xeon
®
Processor 7000 Series
Specifiication Update, March 2010
Implication: This erratum may cause a load to an unexpected memory address.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
A76. Attempting to use an LDT entry when the LDTR has been loaded with
an unusable segment may cause unexpected memory accesses
Problem: In a system supporting Intel® EM64T and Intel Virtualization Technology when the
following occur:
• The LDTR is loaded during VM entry with the segment unusable bit set for the LDTR
in the VMCS.
• The segment limit is non-zero.
• The granularity bit is set references to a segment located in the LDT in 64-bit mode
at any time later may cause the processor to exhibit unexpected behavior.
Implication: This erratum may cause unexpected memory accesses.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
A77. FS/GS base MSRs can be loaded from MSR-load areas during VM entry
or VM exit
Problem: If the VM exit or VM entry MSR-load area contains references to the FS or GS Base
MSRs, the VM exit and VM entry transitions should fail. Instead, the operation will load
the MSRs with the value in the corresponding MSR-load area entry.
Implication: VM entries and VM exits that should fail will complete successfully in this situation. If a
VM entry is to virtual-8086 mode, the base address for FS or for GS may be loaded with
a value that is not consistent with that mode. Intel has not observed this erratum with
any commercially available software or systems.
Workaround: Software should not enter values in the MSR-load areas that correspond to either the
FS base MSR or the GS base MSR. Software can establish the value of these registers
on VM entry using the guest-state area of the VMCS and on VM exit using the host-
state area of the VMCS.
Status: For the steppings affected, see the Summary Table of Changes.
A78. NMI-blocking information recorded in VMCS may be incorrect after a
#GP on an IRET instruction
Problem: In a system supporting Intel Virtualization Technology, the NMI blocking bit in the
Interruption-Information field in the guest VMCS may be set incorrectly. This erratum
will happen if a VM exit occurs for a #GP fault on an IRET instruction due to an EIP that
violates the segment limit or is non-canonical.
Implication: If this erratum occurs, monitor software may not be able to handle #GP and then inject
an NMI since monitor software does not have information about whether NMIs are
blocked in the guest.
Workaround: Monitor software can workaround this bug by avoiding injection of NMI after #GP
emulation.
Status: For the steppings affected, see the Summary Table of Changes.
A79. VMLAUNCH/VMRESUME may not fail when VMCS is programmed to
cause VM exit to return to a different mode
Problem: VMLAUNCH/VMRESUME instructions may not fail if the value of the “host address-space
size” VM exit control differs from the setting of IA32_EFER.LMA.
Implication: Programming the VMCS to allow the monitor to be in different modes prior to
VMLAUNCH/VMRESUME and after VM exit may result in undefined behavior.