Specification Update

34 Intel
®
Xeon
®
Processor 7000 Series
Specifiication Update, March 2010
can only occur if the IRET instruction is returning from CPL3 code to CPL3 code. IRETs
from CPL0/1/2 are not affected. This erratum can occur if the EFLAGS value on the
stack has the AC flag set, and the interrupt handler's stack is misaligned. In IA-32e
mode, RSP is aligned to a 16-byte boundary before pushing the stack frame.
Implication: In IA-32e mode, under the conditions given above, an IRET can get a #AC even if
alignment checks are disabled at the start of the IRET. This erratum can only be
observed with a software generated stack frame.
Workaround: Software should not generate misaligned stack frames for use with IRET.
Status: For the steppings affected, see the Summary Table of Changes.
A58. Running with Virtual Machine Extensions (VMX) in L1 data cache
adaptive mode may cause unexpected system behavior
Problem: In a system supporting Hyper-Threading Technology and Intel
®
Virtualization
Technology, unexpected system behavior may result if a change to the value of CR0,
CR3 and CR4 occurs during a VM entry or VM exit operation while in L1 data
cache adaptive mode (IA32_MISC_ENABLES MSR 0x1a0 bit 24).
Implication: This erratum can have multiple failure symptoms including incorrect data in memory.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
A59. A mispredicted branch may issue a speculative load to an incorrect
address during VM exit on processors supporting Intel
®
Virtualization
Technology
Problem: During VM exit on processors supporting Intel Virtualization Technology, a mispredicted
branch may result in a speculative load to an incorrect address.
Implication: This erratum may cause access to an incorrect address space during VM exit.
Workaround: It is possible for BIOS to have a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
A60. Exit qualification and pending debug exceptions Virtual-Machine
Control Structure (VMCS) fields contain incorrect information on VM
exits due to debug exceptions
Problem: In systems supporting Intel Virtualization Technology, a debug exception which
causes a VM exit may cause incorrect information to be loaded into the pending debug
exceptions and the Exit Qualification fields of the Virtual-Machine Control Structure
(VMCS).
Implication: When executing code using debug breakpoints, host software may see incorrect
information in these fields of the VMCS.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
A61. VM exit saves incorrect interruptibility state information on exit due to
nested exceptions
Problem: VM exit does not save Interruptibility State field Bits[1:0] as 0 on an exit due to nested
exception or double fault or triple fault. The VM exit may save spurious information
about events that are being blocked by STI and MOVSS/POPSS instructions.
Implication: The Interruptibility State field Bits[1:0] may not contain appropriate state of guest
events being blocked by STI or MOVSS/POPSS instruction.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.