Specification Update

Intel
®
Xeon
®
Processor 7000 Series 33
Specification Update, March 2010
system may be susceptible to a variety of failing symptoms including; system hangs
and MCERR# or IERR# assertions.
Implication: POC can not be used to enter single logical processor mode.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
A54. Machine check exception may be signaled in a system with multiple
threads and several lock transactions
Problem: The processor assumes the central agent is responsible for forward progress once it has
retried a request. The central agent attempts to guarantee forward progress to each
bus agent by periodically providing a slot where the requester can drive a transaction
that will not get retried. The central agent does not track progress on a per thread
basis. When the following conditions are met, it is possible for one thread to not make
forward progress and result in a fatal machine check exception.
1. One agent performs repeated bus lock requests.
2. Another agent performs repeated cache locks and also performs a code fetch for
the other thread.
Implication: Due to this erratum, the processor may generate a fatal Machine Check Exception with
a time-out exception error code.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
A55. The processor may issue multiple code fetches to the same cache line
for systems with slow memory
Problem: Systems with long latencies on returning code fetch data from memory e.g., BIOS
ROM, may cause the processor to issue multiple fetches to the same cache line, once
per each instruction executed.
Implication: This erratum may slow down system boot time. Intel has not observed a failure, as a
result of this erratum, in a commercially available system.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
A56. Writing the local vector table (LVT) when an interrupt is pending may
cause an unexpected interrupt
Problem: If a local interrupt is pending when the LVT entry is written, an interrupt may be
taken on the new interrupt vector even if the mask bit is set.
Implication: An interrupt may immediately be generated with the new vector when a LVT entry is
written, even if the new LVT entry has the mask bit set. If there is no interrupt service
routine (ISR) set up for that vector the system will GP fault. If the ISR does not do an
end of interrupt (EOI) the bit for the vector will be left set in the in-service register and
mask all interrupts at the same or lower priority.
Workaround: Any vector programmed into an LVT entry must have an ISR associated with it, even if
that vector was programmed as masked. This ISR routine must do an EOI to clear any
unexpected interrupts that may occur. The ISR associated with the spurious vector
does not generate an EOI, therefore the spurious vector should not be used when
writing the LVT.
Status: For the steppings affected, see the Summary Table of Changes.
A57. IRET under certain conditions may cause an unexpected alignment
check exception
Problem: In IA-32e mode, it is possible to get an alignment check exception (#AC) on the IRET
instruction even though alignment checks were disabled at the start of the IRET. This