Hub Datasheet

98 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.7 PCI-to-AGP Bridge Registers (Device 1, Function 0)
The PCI-to-AGP registers are in Device 1 (D1), Function 0 (F0). Table 3-5 provides the register
address map for this device, function.
Warning: Address locations that are not listed the table are considered reserved register locations. Writes to
“Reserved” registers may cause system failure. Reads to “Reserved” registers may return a non-
zero value.
Table 3-5. PCI-to-AGP Bridge Register Address Map (D1:F0)
Address
Offset
Mnemonic Register Name
Default
Value
Access
00–01h VID1 Vendor Identification 8086h RO
02–03h DID1 Device Identification 2552h RO
04–05h PCICMD1 PCI Command 0000h RO, RW
06–07h PCISTS1 PCI Status 00B0h R/WC, RO
08h RID1 Revision Identification
See register
description
RO
0Ah SUBC1 Sub Class Code 04h RO
0Bh BCC1 Base Class Code 06h RO
0Dh MLT1 Master Latency Timer 00h RO,RW
0Eh HDR1 Header Type 01h RO
10–13h APBASELO AGP Aperture Base Address 0000 0008h RO,RW
18h PBUSN1 Primary Bus Number 00h RO
19h SBUSN1 Secondary Bus Number 00h RW
1Ah SUBUSN1 Subordinate Bus Number 00h RW
1Bh SMLT1 Secondary Bus Master Latency Timer 00h RO,RW
1Ch IOBASE1 I/O Base Address F0h RO,RW
1Dh IOLIMIT1 I/O Limit Address 00h RO,RW
1E–1Fh SSTS1 Secondary Status 02A0h RW
20–21h MBASE1 Memory Base Address FFF0h RO, RW
22–23h MLIMIT1 Memory Limit Address 0000h RO, RW
24–25h PMBASE1 Prefetchable Memory Base Address FFF0h RO, RW
26–27h PMLIMIT1 Prefetchable Memory Limit Address 0000h RO, RW
34h CAPPTR Capabilities Pointer 60h RO
3Eh BCTRL1 Bridge Control 00h RO, RW
40h ERRCMD1 Error Command 00h RO, RW
42h ERRSTS1 Error Status 00h RO, R/WC
60–63h AGPCAPID1 AGP Capability Identifier 0035 0002h RO
64–67h AGPSTAT1 AGP Status 1F00 xx1xh RO
68–6Bh AGPCMD AGP Command 0000 0000h RO, RW
70–73h AGPCTR1L AGP Control Register 0000 0000h RO, RW
74–75h APSIZE1 AGP Aperture Size 0000h RO, RW
78–7Bh ATTBASE1 AGP GART Pointer 0000 0000h RO, RW