Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 45
Register Description
3.5 Chipset Host Controller Registers (Device 0,
Function 0)
The Chipset Host Controller registers are in Device 0 (D0), Function 0 (F0). Table 3-2 provides the
register address map for this device, function.
Warning: Address locations that are not listed the table are considered reserved register locations. Writes to
“Reserved” registers may cause system failure. Reads to “Reserved” registers may return a non-
zero value.
Table 3-2. Chipset Host Controller Register Address Map (D0:F0)
Address
Offset
Mnemonic Register Name
Default
Value
Access
00–01h VID Vendor Identification 8086h RO
02–03h DID Device Identification 2550h RO
04–05h PCICMD PCI Command Register 0006h RO, RW
06–07h PCISTS PCI Status Register 0090h R/WC, RO
08h RID Revision Identification
see register
description
RO
0Ah SUBC Sub Class Code 00h RO
0Bh BCC Base Class Code 00h RO
0Dh MLT Master Latency Timer 06h RO
0Eh HDR Header Type 00h RO
10–13h APBASE Aperture Base Config 0000 0008h RO, RW
2C–2Dh SVID Subsystem Vendor ID 0000 0000h R/WO
2E–2Fh SID Subsystem Identification 0000h R/WO
34h CAPPTR Capabilities Pointer 40h RO
40–43h CAPID Product Specific Capability Identifier
00 0104
A009h
RO
50–51h MCHCFG MCH Configuration 0004h RO, RW
59–5Fh PAM[0–6] Programmable Attribute Map (7 registers) 00h RO, RW
60–67h DRB DRAM Row Boundary xxh RW
70–73h DRA DRAM Row Attribute 00h RO, RW
78–7Bh DRT DRAM TIming Register 0000 0010h RO
7C–7Fh DRC DRAM Controller Mode 0044 0009h RO, RW
80–81 REROTC
Receive Enable Reference Output Timing
Control Register
00 RW
8Ch CLOCK_DIS CK/CK# Clock Disable FFh
8Eh DDR_CNTL DDR Memory control Register 00xx 0000b
9Dh SMRAM System Management RAM Control 02h RW, RO
9Eh ESMRAMC Extended System Management RAM Control 38h
R/W/L, RW/
C, RO
A0–A3h ACAPID AGP Capability Identifier 0030 0002h RO