Hub Datasheet

42 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.3.1 Logical PCI Bus #0 Configuration Mechanism
The MCH decodes the Bus Number (bits 23:16) and the Device Number fields of the
CONFIG_ADDRESS register. When the Bus Number field of CONFIG_ADDRESS is 0, the
configuration cycle is targeting a PCI Bus #0 device.
The Host-HI_A Bridge entity within the MCH is hardwired as Device 0 on PCI Bus #0
The AGP Bridge entity within the MCH is hardwired as Device 1 on PCI Bus #0.
The Host-HI_B bridge entity within the MCH is hardwired as Device 2 on PCI Bus #0.
Configuration cycles to any of the MCH’s enabled internal devices are confined to the MCH and
not sent over HI_A. Accesses to disabled MCH internal devices are forwarded over HI_A as
Type 0.
The ICH4 decodes the Type 0 access and generates a configuration access to the selected internal
device.
3.3.2 Primary PCI Downstream Configuration Mechanism
When the Bus Number in the CONFIG_ADDRESS is non-zero, and does not lie between the
Secondary Bus Number registers and the Subordinate Bus Number registers for the hub interface,
the MCH generates a type 1 HI_A Configuration Cycle.
When the cycle is forwarded to the ICH4 via HI_A, the ICH4 compares the non-zero Bus Number
with the Secondary Bus Number and Subordinate Bus Number registers of its PCI-to-PCI bridges
to determine if the configuration cycle is meant for Primary PCI, or a downstream PCI bus.
3.3.3 HI_B Bus Configuration Mechanism
From the chipset configuration perspective, HI_B is seen as a PCI bus interface residing on a
Secondary Bus side of the virtual PCI-to-PCI bridge referred to as the MCH Host-HI_B bridge.
When the bus number is non-zero, greater than the value programmed into the Secondary Bus
Number register, and less than or equal to the value programmed into the corresponding
Subordinate Bus Number register, the configuration cycle is targeting a PCI bus downstream of the
targeted hub interface. The MCH generates a Type 1 hub interface configuration cycle on the
appropriate hub interface.