Hub Datasheet

1
Working page only. Do not distribute.
1 Introduction...........................................................................................................15
1.1 Terminology ...................................................................................................15
1.2 Reference Documents ...................................................................................16
1.3 Intel
®
E7505 Chipset System Architecture .................................................... 18
2 Signal Description ..............................................................................................21
2.1 Host Interface Signals.................................................................................... 23
2.2 DDR Channel A Signals.................................................................................26
2.3 DDR Channel B Signals.................................................................................29
2.4 Hub Interface_A Signals ................................................................................ 32
2.5 Hub Interface_B Signals ................................................................................ 32
2.6 AGP Interface Signals....................................................................................33
2.6.1 AGP Arbitration Signals ....................................................................33
2.6.2 AGP Address / Data Signals............................................................. 34
2.6.3 AGP Command/Control Signals .......................................................35
2.7 Clocks, Reset, and Miscellaneous Signals .................................................... 37
2.8 Strap Signals..................................................................................................38
3 Register Description.......................................................................................... 39
3.1 Register Nomenclature and Access Attributes ..............................................39
3.2 PCI Configuration Space Access...................................................................40
3.2.1 PCI Bus Configuration Mechanism ................................................... 41
3.3 General Routing Configuration Accesses ......................................................41
3.3.1 Logical PCI Bus #0 Configuration Mechanism..................................42
3.3.2 Primary PCI Downstream Configuration Mechanism........................42
3.3.3 HI_B Bus Configuration Mechanism ................................................. 42
3.3.4 AGP Bus Configuration Mechanism .................................................43
3.4 I/O Mapped Registers ....................................................................................43
3.4.1 CONFIG_ADDRESS—Configuration Address Register ...................44
3.4.2 CONFIG_DATA—Configuration Data Register ................................44
3.5 Chipset Host Controller Registers (Device 0, Function 0) .............................45
3.5.1 VID—Vendor Identification Register (D0:F0) .................................... 46
3.5.2 DID—Device Identification Register (D0:F0) .................................... 46
3.5.3 PCICMD—PCI Command Register (D0:F0) .....................................47
3.5.4 PCISTS—PCI Status Register (D0:F0).............................................48
3.5.5 RID—Revision Identification Register (D0:F0).................................. 49
3.5.6 SUBC—Sub-Class Code Register (D0:F0)....................................... 49
3.5.7 BCC—Base Class Code Register (D0:F0) .......................................49
3.5.8 MLT—Master Latency Timer Register (D0:F0).................................50
3.5.9 HDR—Header Type Register (D0:F0) .............................................. 50
3.5.10 APBASE—Aperture Base Configuration Register (D0:F0) ...............51
3.5.11 SVID—Subsystem Vendor Identification Register (D0:F0)...............52
3.5.12 SID—Subsystem Identification Register (D0:F0)..............................52
3.5.13 CAPPTR—Capabilities Pointer Register (D0:F0) .............................52
3.5.14 CAPID—Product Specific Capability Identifier Register (D0:F0) ......53
3.5.15 MCHCFG—MCH Configuration Register (D0:F0) ............................54
3.5.16 PAM[0:6]—Programmable Attribute Map Registers (D0:F0) ............56
3.5.17 DRB—DRAM Row Boundary Register (D0:F0) ................................58
3.5.18 DRA—DRAM Row Attribute Register (D0:F0) ..................................60
3.5.19 DRT—DRAM Timing Register (D0:F0) ............................................. 61
3.5.20 DRC—DRAM Controller Mode Register (D0:F0)..............................64