Datasheet

Intel Manageability Engine Subsystem PCI (D3:F0,F3)
202 Datasheet
7.1.21 MA—Message Signaled Interrupt Message Address
B/D/F/Type: 0/3/0/PCI
Address Offset: 90–93h
Default Value: 00000000h
Access: RW, RO
Size: 32 bits
7.1.22 MUA—Message Signaled Interrupt Upper Address
(Optional)
B/D/F/Type: 0/3/0/PCI
Address Offset: 94–97h
Default Value: 00000000h
Access: RW
Size: 32 bits
7.1.23 MD—Message Signaled Interrupt Message Data
B/D/F/Type: 0/3/0/PCI
Address Offset: 98–99h
Default Value: 0000h
Access: RW
Size: 16 bits
Bit Access
Default
Value
Description
31:2 RW
0000000
0h
Address (ADDR): Lower 32 bits of the system specified message address,
always DW aligned.
1:0 RO 00b Reserved
Bit Access
Default
Value
Description
31:0 RW
0000000
0h
Upper Address (UADDR): Upper 32 bits of the system specified message
address. This register is optional and only implemented if MC.C64=1.
Bit Access
Default
Value
Description
15:0 RW 0000h
Data (Data): This 16-bit field is programmed by system software if MSI is
enabled. Its content is driven onto the FSB during the data phase of the MSI
memory write transaction.