Specification Update

Errata
Intel
®
Xeon
®
Processor E7 v2 Product Family 51
Specification Update January 2015
Workaround: A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF132 Configuring PCIe* Port 3a as an NTB Disables EOI Forwarding to Port
2a
Problem: Configuring PCIe Port 3a as an NTB (non-transparent bridge) requires disabling EOI
(End Of Interrupt) broadcast forwarding to this port by setting bit 26 of MISCCTRLSTS
CSR (Bus 0; Device 3; Function 0; Offset 188H) to 0. Due to this erratum, disabling
EOI broadcast forwarding to Port 3a improperly disables EOI broadcast forwarding to
Port 2a.
Implication: Some platform configurations will not behave as expected.
Workaround: If Port 3a is configured as an NTB then devices requiring EOI messages (those using
Message Signaled Interrupts and those with their own IO APIC) must not be connected
to port 2a.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF133 PCIe* LBMS Bit Incorrectly Set
Problem: If a PCIe Link autonomously changes width or speed for reasons other than to attempt
to correct unreliable Link operation, the Port should set LABS bit (Link Autonomous
Bandwidth Status) (Bus 0; Device 0; Function 0 and Device 1; Function 0-1 and Device
2-3; Function 0-3; Offset 0x1A2; bit 15). Due to this erratum, the processor will not set
this bit and will incorrectly set LBMS bit (Link Bandwidth Management Status) (Bus 0;
Device 0; Function 0 and Device 1; Function 0-1 and Device 2-3; Function 0-3; Offset
0x1A2; bit14) instead.
Implication: Software that uses the LBMS bit or LABS bit may behave incorrectly.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF134 PCIe* DLW is Not Supported When Operating at 8 GT/s
Problem: DLW (Dynamic Link Width) is an optional PCIe feature enabling a PCIe device to
dynamically change the link width to manage power and bandwidth. When a PCIe
device is operating at 8 GT/s, an attempt to change the link width using DLW may
result in a Surprise Link Down error.
Implication: Due to this erratum, the processor may experience Surprise Link Down errors.
Workaround: A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF135 Memory Online Request May be Lost When Package C-States Are
Enabled
Problem: When Package C-States are enabled, a request to bring additional memory online may
be ignored.
Implication: When this erratum occurs, additional memory will not be brought online.
Workaround: A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status: For the affected steppings, see the “Summary Table of Changes”.