Specification Update

Errata
26 Intel
®
Xeon
®
Processor E7 v2 Product Family
Specification Update January 2015
Implication: Using DRAM RAPL to regulate the memory subsystem power to a very low level may
cause platform instability.
Workaround: It is possible for the BIOS to contain processor configuration data and code changes as
a workaround for this erratum. the latest version of the BIOS spec update.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF28 TSOD-Related SMBus Transactions may not Complete When Package
C-States are Enabled.
Problem: The processor may not complete SMBus (System Management Bus) transactions
targeting the TSOD (Temperature Sensor On DIMM) when Package C-States are
enabled. Due to this erratum, if the processor transitions into a Package C-State while
an SMBus transaction with the TSOD is in process, the processor will suspend receipt of
the transaction. The transaction completes while the processor is in a Package C-State.
Upon exiting Package C-State, the processor will attempt to resume the SMBus
transaction, detect a protocol violation, and log an error.
Implication: When Package C-States are enabled, the SMBus communication error rate between the
processor and the TSOD may be higher than expected.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF29 The Integrated Memory Controller does not Enforce CKE High For
tXSDLL DCLKs After Self-Refresh.
Problem: The JEDEC STANDARD DDR3 SDRAM Specification (No. 79-3E) requires that the CKE
signal be held high for tXSDLL DCLKs after exiting self-refresh before issuing
commands that require a locked DLL (Delay-Locked Loop). Due to this erratum, the
Integrated Memory Controller may not meet this requirement with 512 Mb, 1 Gb, and
2 Gb devices in single rank per channel configurations.
Implication: Violating tXSDLL may result in DIMM clocking issues and may lead to unpredictable
system behavior.
Workaround: A BIOS workaround has been identified. Refer to Intel® Xeon® Processor E7 v2
Product Family-based platform CPU/Intel
®
QPI/Memory Reference Code version 1.0 or
later and release notes.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF30 Intel
®
QuickData Technology DMA Suspend does not Transition From
ARMED to HALT State.
Problem: Suspending an Intel
®
QuickData Technology DMA channel while in the ARMED state
should transition the channel to the HALT state. Due to this erratum, suspending a DMA
channel while in the ARMED state does not change the state to HALT and will cause the
DMA engine, when subsequently activated, to ignore the first descriptor's fence control
bit and may cause the DMA engine to prematurely discard the first descriptor during
the copy stage.
Implication: Suspending a DMA channel while in the ARMED state will cause the DMA engine to
ignore descriptor fencing, possibly issue completion status without actually completing
all descriptors, and may be subject to unexpected activation of DMA transfers.
Workaround: Check the DMA_trans_state (CHANSTS_0; Bus 0; MMIO BAR: CB_BAR [0:7]; Offset
88H; bits[2:0]) to ensure the channel state is either IDLE (001b) or ACTIVE
(000b) before setting Susp_DMA (CHANCMD; Bus 0; MMIO BAR: CB_BAR [0:7]; Offset
84H;bit 2).
Status: For the affected steppings, see the “Summary Table of Changes”.